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1 ============================
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2 User Guide for R600 Back-end
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3 ============================
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4
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5 Introduction
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6 ============
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7
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8 The R600 back-end provides ISA code generation for AMD GPUs, starting with
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9 the R600 family up until the current Sea Islands (GCN Gen 2).
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10
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11
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12 Assembler
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13 =========
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14
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15 The assembler is currently a work in progress and not yet complete. Below
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16 are the currently supported features.
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17
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18 SOPP Instructions
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19 -----------------
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20
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21 Unless otherwise mentioned, all SOPP instructions that with an operand
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22 accept a integer operand(s) only. No verification is performed on the
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23 operands, so it is up to the programmer to be familiar with the range
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24 or acceptable values.
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25
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26 s_waitcnt
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27 ^^^^^^^^^
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28
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29 s_waitcnt accepts named arguments to specify which memory counter(s) to
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30 wait for.
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31
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32 .. code-block:: nasm
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33
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34 // Wait for all counters to be 0
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35 s_waitcnt 0
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36
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37 // Equivalent to s_waitcnt 0. Counter names can also be delimited by
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38 // '&' or ','.
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39 s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)
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40
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41 // Wait for vmcnt counter to be 1.
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42 s_waitcnt vmcnt(1)
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43
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