annotate lib/CodeGen/AtomicExpandPass.cpp @ 83:60c9769439b8

LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
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1 //===-- AtomicExpandPass.cpp - Expand atomic instructions -------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains a pass (at IR level) to replace atomic instructions with
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11 // either (intrinsic-based) load-linked/store-conditional loops or AtomicCmpXchg.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "llvm/CodeGen/Passes.h"
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16 #include "llvm/IR/Function.h"
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17 #include "llvm/IR/IRBuilder.h"
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18 #include "llvm/IR/InstIterator.h"
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19 #include "llvm/IR/Instructions.h"
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20 #include "llvm/IR/Intrinsics.h"
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21 #include "llvm/IR/Module.h"
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22 #include "llvm/Support/Debug.h"
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23 #include "llvm/Target/TargetLowering.h"
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24 #include "llvm/Target/TargetMachine.h"
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25 #include "llvm/Target/TargetSubtargetInfo.h"
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26
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27 using namespace llvm;
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28
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29 #define DEBUG_TYPE "atomic-expand"
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30
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31 namespace {
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32 class AtomicExpand: public FunctionPass {
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33 const TargetMachine *TM;
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34 const TargetLowering *TLI;
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35 public:
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36 static char ID; // Pass identification, replacement for typeid
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37 explicit AtomicExpand(const TargetMachine *TM = nullptr)
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38 : FunctionPass(ID), TM(TM), TLI(nullptr) {
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39 initializeAtomicExpandPass(*PassRegistry::getPassRegistry());
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40 }
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41
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42 bool runOnFunction(Function &F) override;
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43
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44 private:
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45 bool bracketInstWithFences(Instruction *I, AtomicOrdering Order,
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46 bool IsStore, bool IsLoad);
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47 bool expandAtomicLoad(LoadInst *LI);
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48 bool expandAtomicLoadToLL(LoadInst *LI);
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49 bool expandAtomicLoadToCmpXchg(LoadInst *LI);
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50 bool expandAtomicStore(StoreInst *SI);
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51 bool expandAtomicRMW(AtomicRMWInst *AI);
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52 bool expandAtomicRMWToLLSC(AtomicRMWInst *AI);
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53 bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI);
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54 bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
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55 bool isIdempotentRMW(AtomicRMWInst *AI);
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56 bool simplifyIdempotentRMW(AtomicRMWInst *AI);
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57 };
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58 }
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59
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60 char AtomicExpand::ID = 0;
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61 char &llvm::AtomicExpandID = AtomicExpand::ID;
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62 INITIALIZE_TM_PASS(AtomicExpand, "atomic-expand",
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63 "Expand Atomic calls in terms of either load-linked & store-conditional or cmpxchg",
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64 false, false)
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65
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66 FunctionPass *llvm::createAtomicExpandPass(const TargetMachine *TM) {
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67 return new AtomicExpand(TM);
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68 }
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69
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70 bool AtomicExpand::runOnFunction(Function &F) {
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71 if (!TM || !TM->getSubtargetImpl(F)->enableAtomicExpand())
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72 return false;
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73 TLI = TM->getSubtargetImpl(F)->getTargetLowering();
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74
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75 SmallVector<Instruction *, 1> AtomicInsts;
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76
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77 // Changing control-flow while iterating through it is a bad idea, so gather a
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78 // list of all atomic instructions before we start.
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79 for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) {
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80 if (I->isAtomic())
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81 AtomicInsts.push_back(&*I);
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82 }
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83
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84 bool MadeChange = false;
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85 for (auto I : AtomicInsts) {
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86 auto LI = dyn_cast<LoadInst>(I);
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87 auto SI = dyn_cast<StoreInst>(I);
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88 auto RMWI = dyn_cast<AtomicRMWInst>(I);
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89 auto CASI = dyn_cast<AtomicCmpXchgInst>(I);
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90 assert((LI || SI || RMWI || CASI || isa<FenceInst>(I)) &&
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91 "Unknown atomic instruction");
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92
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93 auto FenceOrdering = Monotonic;
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94 bool IsStore, IsLoad;
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95 if (TLI->getInsertFencesForAtomic()) {
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96 if (LI && isAtLeastAcquire(LI->getOrdering())) {
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97 FenceOrdering = LI->getOrdering();
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98 LI->setOrdering(Monotonic);
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99 IsStore = false;
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100 IsLoad = true;
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101 } else if (SI && isAtLeastRelease(SI->getOrdering())) {
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102 FenceOrdering = SI->getOrdering();
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103 SI->setOrdering(Monotonic);
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104 IsStore = true;
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105 IsLoad = false;
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106 } else if (RMWI && (isAtLeastRelease(RMWI->getOrdering()) ||
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107 isAtLeastAcquire(RMWI->getOrdering()))) {
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108 FenceOrdering = RMWI->getOrdering();
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109 RMWI->setOrdering(Monotonic);
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110 IsStore = IsLoad = true;
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111 } else if (CASI && !TLI->hasLoadLinkedStoreConditional() &&
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112 (isAtLeastRelease(CASI->getSuccessOrdering()) ||
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113 isAtLeastAcquire(CASI->getSuccessOrdering()))) {
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114 // If a compare and swap is lowered to LL/SC, we can do smarter fence
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115 // insertion, with a stronger one on the success path than on the
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116 // failure path. As a result, fence insertion is directly done by
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117 // expandAtomicCmpXchg in that case.
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118 FenceOrdering = CASI->getSuccessOrdering();
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119 CASI->setSuccessOrdering(Monotonic);
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120 CASI->setFailureOrdering(Monotonic);
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121 IsStore = IsLoad = true;
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122 }
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123
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124 if (FenceOrdering != Monotonic) {
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125 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad);
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126 }
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127 }
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128
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129 if (LI && TLI->shouldExpandAtomicLoadInIR(LI)) {
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130 MadeChange |= expandAtomicLoad(LI);
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131 } else if (SI && TLI->shouldExpandAtomicStoreInIR(SI)) {
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132 MadeChange |= expandAtomicStore(SI);
83
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133 } else if (RMWI) {
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134 // There are two different ways of expanding RMW instructions:
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135 // - into a load if it is idempotent
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136 // - into a Cmpxchg/LL-SC loop otherwise
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137 // we try them in that order.
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138 MadeChange |=
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139 (isIdempotentRMW(RMWI) && simplifyIdempotentRMW(RMWI)) ||
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140 (TLI->shouldExpandAtomicRMWInIR(RMWI) && expandAtomicRMW(RMWI));
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141 } else if (CASI && TLI->hasLoadLinkedStoreConditional()) {
77
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142 MadeChange |= expandAtomicCmpXchg(CASI);
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143 }
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diff changeset
144 }
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145 return MadeChange;
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146 }
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147
83
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148 bool AtomicExpand::bracketInstWithFences(Instruction *I, AtomicOrdering Order,
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149 bool IsStore, bool IsLoad) {
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150 IRBuilder<> Builder(I);
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151
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152 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad);
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153
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154 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad);
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155 // The trailing fence is emitted before the instruction instead of after
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156 // because there is no easy way of setting Builder insertion point after
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157 // an instruction. So we must erase it from the BB, and insert it back
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158 // in the right place.
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159 // We have a guard here because not every atomic operation generates a
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160 // trailing fence.
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161 if (TrailingFence) {
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162 TrailingFence->removeFromParent();
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163 TrailingFence->insertAfter(I);
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164 }
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165
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166 return (LeadingFence || TrailingFence);
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167 }
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168
77
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169 bool AtomicExpand::expandAtomicLoad(LoadInst *LI) {
83
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170 if (TLI->hasLoadLinkedStoreConditional())
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171 return expandAtomicLoadToLL(LI);
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172 else
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173 return expandAtomicLoadToCmpXchg(LI);
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174 }
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175
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176 bool AtomicExpand::expandAtomicLoadToLL(LoadInst *LI) {
77
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177 IRBuilder<> Builder(LI);
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178
83
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179 // On some architectures, load-linked instructions are atomic for larger
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180 // sizes than normal loads. For example, the only 64-bit load guaranteed
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181 // to be single-copy atomic by ARM is an ldrexd (A3.5.3).
77
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182 Value *Val =
83
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183 TLI->emitLoadLinked(Builder, LI->getPointerOperand(), LI->getOrdering());
77
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184
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185 LI->replaceAllUsesWith(Val);
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186 LI->eraseFromParent();
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187
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188 return true;
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189 }
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190
83
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191 bool AtomicExpand::expandAtomicLoadToCmpXchg(LoadInst *LI) {
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192 IRBuilder<> Builder(LI);
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193 AtomicOrdering Order = LI->getOrdering();
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194 Value *Addr = LI->getPointerOperand();
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195 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
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196 Constant *DummyVal = Constant::getNullValue(Ty);
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197
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198 Value *Pair = Builder.CreateAtomicCmpXchg(
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199 Addr, DummyVal, DummyVal, Order,
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200 AtomicCmpXchgInst::getStrongestFailureOrdering(Order));
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201 Value *Loaded = Builder.CreateExtractValue(Pair, 0, "loaded");
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202
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203 LI->replaceAllUsesWith(Loaded);
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204 LI->eraseFromParent();
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diff changeset
205
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206 return true;
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207 }
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diff changeset
208
77
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diff changeset
209 bool AtomicExpand::expandAtomicStore(StoreInst *SI) {
83
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210 // This function is only called on atomic stores that are too large to be
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diff changeset
211 // atomic if implemented as a native store. So we replace them by an
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diff changeset
212 // atomic swap, that can be implemented for example as a ldrex/strex on ARM
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diff changeset
213 // or lock cmpxchg8/16b on X86, as these are atomic for larger sizes.
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diff changeset
214 // It is the responsibility of the target to only return true in
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diff changeset
215 // shouldExpandAtomicRMW in cases where this is required and possible.
77
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diff changeset
216 IRBuilder<> Builder(SI);
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diff changeset
217 AtomicRMWInst *AI =
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diff changeset
218 Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, SI->getPointerOperand(),
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diff changeset
219 SI->getValueOperand(), SI->getOrdering());
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diff changeset
220 SI->eraseFromParent();
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parents:
diff changeset
221
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222 // Now we have an appropriate swap instruction, lower it as usual.
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diff changeset
223 return expandAtomicRMW(AI);
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diff changeset
224 }
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parents:
diff changeset
225
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diff changeset
226 bool AtomicExpand::expandAtomicRMW(AtomicRMWInst *AI) {
83
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diff changeset
227 if (TLI->hasLoadLinkedStoreConditional())
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diff changeset
228 return expandAtomicRMWToLLSC(AI);
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diff changeset
229 else
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diff changeset
230 return expandAtomicRMWToCmpXchg(AI);
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diff changeset
231 }
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diff changeset
232
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233 /// Emit IR to implement the given atomicrmw operation on values in registers,
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diff changeset
234 /// returning the new value.
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235 static Value *performAtomicOp(AtomicRMWInst::BinOp Op, IRBuilder<> &Builder,
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diff changeset
236 Value *Loaded, Value *Inc) {
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diff changeset
237 Value *NewVal;
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diff changeset
238 switch (Op) {
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diff changeset
239 case AtomicRMWInst::Xchg:
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diff changeset
240 return Inc;
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diff changeset
241 case AtomicRMWInst::Add:
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242 return Builder.CreateAdd(Loaded, Inc, "new");
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diff changeset
243 case AtomicRMWInst::Sub:
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diff changeset
244 return Builder.CreateSub(Loaded, Inc, "new");
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diff changeset
245 case AtomicRMWInst::And:
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diff changeset
246 return Builder.CreateAnd(Loaded, Inc, "new");
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diff changeset
247 case AtomicRMWInst::Nand:
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diff changeset
248 return Builder.CreateNot(Builder.CreateAnd(Loaded, Inc), "new");
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diff changeset
249 case AtomicRMWInst::Or:
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diff changeset
250 return Builder.CreateOr(Loaded, Inc, "new");
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diff changeset
251 case AtomicRMWInst::Xor:
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diff changeset
252 return Builder.CreateXor(Loaded, Inc, "new");
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diff changeset
253 case AtomicRMWInst::Max:
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diff changeset
254 NewVal = Builder.CreateICmpSGT(Loaded, Inc);
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diff changeset
255 return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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diff changeset
256 case AtomicRMWInst::Min:
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diff changeset
257 NewVal = Builder.CreateICmpSLE(Loaded, Inc);
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diff changeset
258 return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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diff changeset
259 case AtomicRMWInst::UMax:
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diff changeset
260 NewVal = Builder.CreateICmpUGT(Loaded, Inc);
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diff changeset
261 return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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diff changeset
262 case AtomicRMWInst::UMin:
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parents: 77
diff changeset
263 NewVal = Builder.CreateICmpULE(Loaded, Inc);
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264 return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
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265 default:
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266 llvm_unreachable("Unknown atomic op");
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267 }
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268 }
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269
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270 bool AtomicExpand::expandAtomicRMWToLLSC(AtomicRMWInst *AI) {
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271 AtomicOrdering MemOpOrder = AI->getOrdering();
77
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272 Value *Addr = AI->getPointerOperand();
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273 BasicBlock *BB = AI->getParent();
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274 Function *F = BB->getParent();
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275 LLVMContext &Ctx = F->getContext();
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276
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277 // Given: atomicrmw some_op iN* %addr, iN %incr ordering
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278 //
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279 // The standard expansion we produce is:
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280 // [...]
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281 // fence?
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282 // atomicrmw.start:
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283 // %loaded = @load.linked(%addr)
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284 // %new = some_op iN %loaded, %incr
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285 // %stored = @store_conditional(%new, %addr)
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286 // %try_again = icmp i32 ne %stored, 0
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287 // br i1 %try_again, label %loop, label %atomicrmw.end
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288 // atomicrmw.end:
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289 // fence?
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290 // [...]
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291 BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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292 BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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293
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294 // This grabs the DebugLoc from AI.
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295 IRBuilder<> Builder(AI);
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296
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297 // The split call above "helpfully" added a branch at the end of BB (to the
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298 // wrong place), but we might want a fence too. It's easiest to just remove
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299 // the branch entirely.
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300 std::prev(BB->end())->eraseFromParent();
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301 Builder.SetInsertPoint(BB);
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302 Builder.CreateBr(LoopBB);
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303
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304 // Start the main loop block now that we've taken care of the preliminaries.
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305 Builder.SetInsertPoint(LoopBB);
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306 Value *Loaded = TLI->emitLoadLinked(Builder, Addr, MemOpOrder);
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307
83
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308 Value *NewVal =
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309 performAtomicOp(AI->getOperation(), Builder, Loaded, AI->getValOperand());
77
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310
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311 Value *StoreSuccess =
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312 TLI->emitStoreConditional(Builder, NewVal, Addr, MemOpOrder);
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313 Value *TryAgain = Builder.CreateICmpNE(
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314 StoreSuccess, ConstantInt::get(IntegerType::get(Ctx, 32), 0), "tryagain");
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315 Builder.CreateCondBr(TryAgain, LoopBB, ExitBB);
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316
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317 Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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318
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319 AI->replaceAllUsesWith(Loaded);
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320 AI->eraseFromParent();
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321
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322 return true;
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323 }
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324
83
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325 bool AtomicExpand::expandAtomicRMWToCmpXchg(AtomicRMWInst *AI) {
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326 AtomicOrdering MemOpOrder =
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327 AI->getOrdering() == Unordered ? Monotonic : AI->getOrdering();
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328 Value *Addr = AI->getPointerOperand();
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329 BasicBlock *BB = AI->getParent();
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330 Function *F = BB->getParent();
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331 LLVMContext &Ctx = F->getContext();
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332
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333 // Given: atomicrmw some_op iN* %addr, iN %incr ordering
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334 //
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335 // The standard expansion we produce is:
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336 // [...]
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337 // %init_loaded = load atomic iN* %addr
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338 // br label %loop
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339 // loop:
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340 // %loaded = phi iN [ %init_loaded, %entry ], [ %new_loaded, %loop ]
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341 // %new = some_op iN %loaded, %incr
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342 // %pair = cmpxchg iN* %addr, iN %loaded, iN %new
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343 // %new_loaded = extractvalue { iN, i1 } %pair, 0
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344 // %success = extractvalue { iN, i1 } %pair, 1
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345 // br i1 %success, label %atomicrmw.end, label %loop
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346 // atomicrmw.end:
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347 // [...]
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348 BasicBlock *ExitBB = BB->splitBasicBlock(AI, "atomicrmw.end");
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349 BasicBlock *LoopBB = BasicBlock::Create(Ctx, "atomicrmw.start", F, ExitBB);
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350
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351 // This grabs the DebugLoc from AI.
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352 IRBuilder<> Builder(AI);
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353
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354 // The split call above "helpfully" added a branch at the end of BB (to the
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355 // wrong place), but we want a load. It's easiest to just remove
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356 // the branch entirely.
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357 std::prev(BB->end())->eraseFromParent();
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358 Builder.SetInsertPoint(BB);
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359 LoadInst *InitLoaded = Builder.CreateLoad(Addr);
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360 // Atomics require at least natural alignment.
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361 InitLoaded->setAlignment(AI->getType()->getPrimitiveSizeInBits());
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362 Builder.CreateBr(LoopBB);
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diff changeset
363
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364 // Start the main loop block now that we've taken care of the preliminaries.
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365 Builder.SetInsertPoint(LoopBB);
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366 PHINode *Loaded = Builder.CreatePHI(AI->getType(), 2, "loaded");
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367 Loaded->addIncoming(InitLoaded, BB);
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diff changeset
368
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369 Value *NewVal =
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370 performAtomicOp(AI->getOperation(), Builder, Loaded, AI->getValOperand());
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diff changeset
371
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372 Value *Pair = Builder.CreateAtomicCmpXchg(
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373 Addr, Loaded, NewVal, MemOpOrder,
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374 AtomicCmpXchgInst::getStrongestFailureOrdering(MemOpOrder));
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375 Value *NewLoaded = Builder.CreateExtractValue(Pair, 0, "newloaded");
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376 Loaded->addIncoming(NewLoaded, LoopBB);
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diff changeset
377
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378 Value *Success = Builder.CreateExtractValue(Pair, 1, "success");
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379 Builder.CreateCondBr(Success, ExitBB, LoopBB);
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diff changeset
380
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381 Builder.SetInsertPoint(ExitBB, ExitBB->begin());
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diff changeset
382
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383 AI->replaceAllUsesWith(NewLoaded);
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384 AI->eraseFromParent();
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diff changeset
385
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386 return true;
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387 }
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diff changeset
388
77
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diff changeset
389 bool AtomicExpand::expandAtomicCmpXchg(AtomicCmpXchgInst *CI) {
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diff changeset
390 AtomicOrdering SuccessOrder = CI->getSuccessOrdering();
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diff changeset
391 AtomicOrdering FailureOrder = CI->getFailureOrdering();
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diff changeset
392 Value *Addr = CI->getPointerOperand();
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diff changeset
393 BasicBlock *BB = CI->getParent();
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diff changeset
394 Function *F = BB->getParent();
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395 LLVMContext &Ctx = F->getContext();
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diff changeset
396 // If getInsertFencesForAtomic() returns true, then the target does not want
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 // to deal with memory orders, and emitLeading/TrailingFence should take care
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 // of everything. Otherwise, emitLeading/TrailingFence are no-op and we
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 // should preserve the ordering.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 AtomicOrdering MemOpOrder =
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
401 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
402
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 // Given: cmpxchg some_op iN* %addr, iN %desired, iN %new success_ord fail_ord
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 //
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 // The full expansion we produce is:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 // [...]
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 // fence?
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 // cmpxchg.start:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 // %loaded = @load.linked(%addr)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 // %should_store = icmp eq %loaded, %desired
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 // br i1 %should_store, label %cmpxchg.trystore,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 // label %cmpxchg.failure
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 // cmpxchg.trystore:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 // %stored = @store_conditional(%new, %addr)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 // %success = icmp eq i32 %stored, 0
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 // br i1 %success, label %cmpxchg.success, label %loop/%cmpxchg.failure
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
417 // cmpxchg.success:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 // fence?
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
419 // br label %cmpxchg.end
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 // cmpxchg.failure:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 // fence?
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 // br label %cmpxchg.end
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 // cmpxchg.end:
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 // %success = phi i1 [true, %cmpxchg.success], [false, %cmpxchg.failure]
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 // %restmp = insertvalue { iN, i1 } undef, iN %loaded, 0
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 // %res = insertvalue { iN, i1 } %restmp, i1 %success, 1
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 // [...]
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 BasicBlock *ExitBB = BB->splitBasicBlock(CI, "cmpxchg.end");
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 auto FailureBB = BasicBlock::Create(Ctx, "cmpxchg.failure", F, ExitBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
430 auto SuccessBB = BasicBlock::Create(Ctx, "cmpxchg.success", F, FailureBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
431 auto TryStoreBB = BasicBlock::Create(Ctx, "cmpxchg.trystore", F, SuccessBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 auto LoopBB = BasicBlock::Create(Ctx, "cmpxchg.start", F, TryStoreBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
433
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 // This grabs the DebugLoc from CI
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
435 IRBuilder<> Builder(CI);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
436
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 // The split call above "helpfully" added a branch at the end of BB (to the
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 // wrong place), but we might want a fence too. It's easiest to just remove
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 // the branch entirely.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 std::prev(BB->end())->eraseFromParent();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 Builder.SetInsertPoint(BB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 TLI->emitLeadingFence(Builder, SuccessOrder, /*IsStore=*/true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 /*IsLoad=*/true);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 Builder.CreateBr(LoopBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 // Start the main loop block now that we've taken care of the preliminaries.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 Builder.SetInsertPoint(LoopBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 Value *Loaded = TLI->emitLoadLinked(Builder, Addr, MemOpOrder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 Value *ShouldStore =
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 Builder.CreateICmpEQ(Loaded, CI->getCompareOperand(), "should_store");
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 // If the the cmpxchg doesn't actually need any ordering when it fails, we can
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 // jump straight past that fence instruction (if it exists).
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 Builder.CreateCondBr(ShouldStore, TryStoreBB, FailureBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
455
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 Builder.SetInsertPoint(TryStoreBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 Value *StoreSuccess = TLI->emitStoreConditional(
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
458 Builder, CI->getNewValOperand(), Addr, MemOpOrder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
459 StoreSuccess = Builder.CreateICmpEQ(
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
460 StoreSuccess, ConstantInt::get(Type::getInt32Ty(Ctx), 0), "success");
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
461 Builder.CreateCondBr(StoreSuccess, SuccessBB,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
462 CI->isWeak() ? FailureBB : LoopBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
464 // Make sure later instructions don't get reordered with a fence if necessary.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
465 Builder.SetInsertPoint(SuccessBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
466 TLI->emitTrailingFence(Builder, SuccessOrder, /*IsStore=*/true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 /*IsLoad=*/true);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 Builder.CreateBr(ExitBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
469
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 Builder.SetInsertPoint(FailureBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 TLI->emitTrailingFence(Builder, FailureOrder, /*IsStore=*/true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 /*IsLoad=*/true);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 Builder.CreateBr(ExitBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
474
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
475 // Finally, we have control-flow based knowledge of whether the cmpxchg
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
476 // succeeded or not. We expose this to later passes by converting any
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
477 // subsequent "icmp eq/ne %loaded, %oldval" into a use of an appropriate PHI.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
478
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
479 // Setup the builder so we can create any PHIs we need.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 Builder.SetInsertPoint(ExitBB, ExitBB->begin());
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 PHINode *Success = Builder.CreatePHI(Type::getInt1Ty(Ctx), 2);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 Success->addIncoming(ConstantInt::getTrue(Ctx), SuccessBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 Success->addIncoming(ConstantInt::getFalse(Ctx), FailureBB);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
484
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
485 // Look for any users of the cmpxchg that are just comparing the loaded value
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
486 // against the desired one, and replace them with the CFG-derived version.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
487 SmallVector<ExtractValueInst *, 2> PrunedInsts;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 for (auto User : CI->users()) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 ExtractValueInst *EV = dyn_cast<ExtractValueInst>(User);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 if (!EV)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 continue;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
492
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 assert(EV->getNumIndices() == 1 && EV->getIndices()[0] <= 1 &&
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 "weird extraction from { iN, i1 }");
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
495
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 if (EV->getIndices()[0] == 0)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 EV->replaceAllUsesWith(Loaded);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 EV->replaceAllUsesWith(Success);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
500
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
501 PrunedInsts.push_back(EV);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
502 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
503
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
504 // We can remove the instructions now we're no longer iterating through them.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 for (auto EV : PrunedInsts)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 EV->eraseFromParent();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
507
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 if (!CI->use_empty()) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 // Some use of the full struct return that we don't understand has happened,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
510 // so we've got to reconstruct it properly.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
511 Value *Res;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
512 Res = Builder.CreateInsertValue(UndefValue::get(CI->getType()), Loaded, 0);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
513 Res = Builder.CreateInsertValue(Res, Success, 1);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
514
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
515 CI->replaceAllUsesWith(Res);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
516 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
517
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 CI->eraseFromParent();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
519 return true;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 }
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
521
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
522 bool AtomicExpand::isIdempotentRMW(AtomicRMWInst* RMWI) {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
523 auto C = dyn_cast<ConstantInt>(RMWI->getValOperand());
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
524 if(!C)
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
525 return false;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
526
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
527 AtomicRMWInst::BinOp Op = RMWI->getOperation();
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
528 switch(Op) {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
529 case AtomicRMWInst::Add:
60c9769439b8 LLVM 3.7
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530 case AtomicRMWInst::Sub:
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531 case AtomicRMWInst::Or:
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532 case AtomicRMWInst::Xor:
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533 return C->isZero();
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534 case AtomicRMWInst::And:
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535 return C->isMinusOne();
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536 // FIXME: we could also treat Min/Max/UMin/UMax by the INT_MIN/INT_MAX/...
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537 default:
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538 return false;
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539 }
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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540 }
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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541
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parents: 77
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542 bool AtomicExpand::simplifyIdempotentRMW(AtomicRMWInst* RMWI) {
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543 if (auto ResultingLoad = TLI->lowerIdempotentRMWIntoFencedLoad(RMWI)) {
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parents: 77
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544 if (TLI->shouldExpandAtomicLoadInIR(ResultingLoad))
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parents: 77
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545 expandAtomicLoad(ResultingLoad);
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546 return true;
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parents: 77
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547 }
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parents: 77
diff changeset
548 return false;
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parents: 77
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549 }