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annotate lib/Target/PowerPC/PPCInstrInfo.h @ 83:60c9769439b8

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 54457678186b
children afa8332a0e37
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
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16
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17 #include "PPC.h"
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18 #include "PPCRegisterInfo.h"
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19 #include "llvm/Target/TargetInstrInfo.h"
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20
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21 #define GET_INSTRINFO_HEADER
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22 #include "PPCGenInstrInfo.inc"
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23
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24 namespace llvm {
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25
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26 /// PPCII - This namespace holds all of the PowerPC target-specific
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27 /// per-instruction flags. These must match the corresponding definitions in
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28 /// PPC.td and PPCInstrFormats.td.
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29 namespace PPCII {
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30 enum {
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31 // PPC970 Instruction Flags. These flags describe the characteristics of the
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32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
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33 // raw machine instructions.
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34
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35 /// PPC970_First - This instruction starts a new dispatch group, so it will
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36 /// always be the first one in the group.
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37 PPC970_First = 0x1,
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38
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39 /// PPC970_Single - This instruction starts a new dispatch group and
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40 /// terminates it, so it will be the sole instruction in the group.
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41 PPC970_Single = 0x2,
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42
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43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
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44 /// two dispatch pipes to be available to issue.
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45 PPC970_Cracked = 0x4,
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46
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47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
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48 /// an instruction is issued to.
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49 PPC970_Shift = 3,
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50 PPC970_Mask = 0x07 << PPC970_Shift
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51 };
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52 enum PPC970_Unit {
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53 /// These are the various PPC970 execution unit pipelines. Each instruction
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54 /// is one of these.
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55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
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56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
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57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
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58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
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59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
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60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
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61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
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62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
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63 };
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64 } // end namespace PPCII
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65
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66
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67 class PPCInstrInfo : public PPCGenInstrInfo {
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68 PPCSubtarget &Subtarget;
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69 const PPCRegisterInfo RI;
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70
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71 bool StoreRegToStackSlot(MachineFunction &MF,
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72 unsigned SrcReg, bool isKill, int FrameIdx,
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73 const TargetRegisterClass *RC,
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74 SmallVectorImpl<MachineInstr*> &NewMIs,
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75 bool &NonRI, bool &SpillsVRS) const;
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76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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77 unsigned DestReg, int FrameIdx,
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78 const TargetRegisterClass *RC,
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79 SmallVectorImpl<MachineInstr*> &NewMIs,
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80 bool &NonRI, bool &SpillsVRS) const;
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81 virtual void anchor();
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82 public:
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83 explicit PPCInstrInfo(PPCSubtarget &STI);
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84
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85 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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86 /// such, whenever a client has an instance of instruction info, it should
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87 /// always be able to get register info as well (through this method).
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88 ///
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89 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
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90
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91 ScheduleHazardRecognizer *
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92 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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93 const ScheduleDAG *DAG) const override;
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94 ScheduleHazardRecognizer *
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95 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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96 const ScheduleDAG *DAG) const override;
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97
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98 int getOperandLatency(const InstrItineraryData *ItinData,
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99 const MachineInstr *DefMI, unsigned DefIdx,
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100 const MachineInstr *UseMI,
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101 unsigned UseIdx) const override;
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102 int getOperandLatency(const InstrItineraryData *ItinData,
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103 SDNode *DefNode, unsigned DefIdx,
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104 SDNode *UseNode, unsigned UseIdx) const override {
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105 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
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106 UseNode, UseIdx);
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107 }
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108
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109 bool hasLowDefLatency(const InstrItineraryData *ItinData,
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110 const MachineInstr *DefMI,
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111 unsigned DefIdx) const override {
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112 // Machine LICM should hoist all instructions in low-register-pressure
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113 // situations; none are sufficiently free to justify leaving in a loop
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114 // body.
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115 return false;
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116 }
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117
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118 bool isCoalescableExtInstr(const MachineInstr &MI,
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119 unsigned &SrcReg, unsigned &DstReg,
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120 unsigned &SubIdx) const override;
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121 unsigned isLoadFromStackSlot(const MachineInstr *MI,
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122 int &FrameIndex) const override;
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123 unsigned isStoreToStackSlot(const MachineInstr *MI,
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124 int &FrameIndex) const override;
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125
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126 // commuteInstruction - We can commute rlwimi instructions, but only if the
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127 // rotate amt is zero. We also have to munge the immediates a bit.
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128 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
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129
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130 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
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131 unsigned &SrcOpIdx2) const override;
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132
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133 void insertNoop(MachineBasicBlock &MBB,
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134 MachineBasicBlock::iterator MI) const override;
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135
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136
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137 // Branch analysis.
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138 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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139 MachineBasicBlock *&FBB,
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140 SmallVectorImpl<MachineOperand> &Cond,
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141 bool AllowModify) const override;
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142 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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143 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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144 MachineBasicBlock *FBB,
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145 const SmallVectorImpl<MachineOperand> &Cond,
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146 DebugLoc DL) const override;
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147
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148 // Select analysis.
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149 bool canInsertSelect(const MachineBasicBlock&,
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150 const SmallVectorImpl<MachineOperand> &Cond,
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151 unsigned, unsigned, int&, int&, int&) const override;
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152 void insertSelect(MachineBasicBlock &MBB,
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153 MachineBasicBlock::iterator MI, DebugLoc DL,
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154 unsigned DstReg,
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155 const SmallVectorImpl<MachineOperand> &Cond,
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156 unsigned TrueReg, unsigned FalseReg) const override;
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157
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158 void copyPhysReg(MachineBasicBlock &MBB,
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159 MachineBasicBlock::iterator I, DebugLoc DL,
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160 unsigned DestReg, unsigned SrcReg,
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161 bool KillSrc) const override;
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162
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163 void storeRegToStackSlot(MachineBasicBlock &MBB,
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164 MachineBasicBlock::iterator MBBI,
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165 unsigned SrcReg, bool isKill, int FrameIndex,
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166 const TargetRegisterClass *RC,
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167 const TargetRegisterInfo *TRI) const override;
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168
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169 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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170 MachineBasicBlock::iterator MBBI,
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171 unsigned DestReg, int FrameIndex,
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172 const TargetRegisterClass *RC,
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173 const TargetRegisterInfo *TRI) const override;
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174
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175 bool
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176 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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177
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178 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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179 unsigned Reg, MachineRegisterInfo *MRI) const override;
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180
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181 // If conversion by predication (only supported by some branch instructions).
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182 // All of the profitability checks always return true; it is always
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183 // profitable to use the predicated branches.
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184 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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185 unsigned NumCycles, unsigned ExtraPredCycles,
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186 const BranchProbability &Probability) const override {
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187 return true;
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188 }
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189
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190 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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191 unsigned NumT, unsigned ExtraT,
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192 MachineBasicBlock &FMBB,
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193 unsigned NumF, unsigned ExtraF,
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194 const BranchProbability &Probability) const override;
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195
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196 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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197 unsigned NumCycles,
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198 const BranchProbability
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199 &Probability) const override {
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200 return true;
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201 }
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202
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203 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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204 MachineBasicBlock &FMBB) const override {
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205 return false;
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206 }
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207
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208 // Predication support.
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209 bool isPredicated(const MachineInstr *MI) const override;
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210
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211 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
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212
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213 bool PredicateInstruction(MachineInstr *MI,
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214 const SmallVectorImpl<MachineOperand> &Pred) const override;
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215
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216 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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217 const SmallVectorImpl<MachineOperand> &Pred2) const override;
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218
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219 bool DefinesPredicate(MachineInstr *MI,
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220 std::vector<MachineOperand> &Pred) const override;
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221
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222 bool isPredicable(MachineInstr *MI) const override;
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223
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224 // Comparison optimization.
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225
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226
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227 bool analyzeCompare(const MachineInstr *MI,
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228 unsigned &SrcReg, unsigned &SrcReg2,
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229 int &Mask, int &Value) const override;
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230
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231 bool optimizeCompareInstr(MachineInstr *CmpInstr,
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232 unsigned SrcReg, unsigned SrcReg2,
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233 int Mask, int Value,
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234 const MachineRegisterInfo *MRI) const override;
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235
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236 /// GetInstSize - Return the number of bytes of code the specified
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237 /// instruction may be. This returns the maximum number of bytes.
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238 ///
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239 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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240
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241 void getNoopForMachoTarget(MCInst &NopInst) const override;
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242 };
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243
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244 }
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245
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246 #endif