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annotate test/CodeGen/ARM/alloc-no-stack-realign.ll @ 83:60c9769439b8

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LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Wed, 18 Feb 2015 14:55:36 +0900
parents 95c75e76d11b
children afa8332a0e37
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95c75e76d11b LLVM 3.4
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1 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN
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2 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN
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3
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4 ; rdar://12713765
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5 ; When realign-stack is set to false, make sure we are not creating stack
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6 ; objects that are assumed to be 64-byte aligned.
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7 @T3_retval = common global <16 x float> zeroinitializer, align 16
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8
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9 define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
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10 entry:
83
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11 ; NO-REALIGN-LABEL: test1
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12 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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13 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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14 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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15 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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16 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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17 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
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18 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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19
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20 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
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21 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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22 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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23 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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24 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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25 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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26 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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27
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28 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
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29 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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30 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
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31 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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32 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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33 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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34 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
0
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35 %retval = alloca <16 x float>, align 16
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36 %0 = load <16 x float>* @T3_retval, align 16
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37 store <16 x float> %0, <16 x float>* %retval
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38 %1 = load <16 x float>* %retval
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39 store <16 x float> %1, <16 x float>* %agg.result, align 16
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40 ret void
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41 }
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42
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43 define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
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44 entry:
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45 ; REALIGN-LABEL: test2
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46 ; REALIGN: bfc sp, #0, #6
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47 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
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48 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
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49 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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50 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
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51 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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52 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
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53 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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54
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55
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56 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
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57 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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58 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32
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59 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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60 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16
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61 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
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62 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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63
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64 ; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48
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65 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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66 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
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67 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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68 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
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69 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
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70 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
0
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71 %retval = alloca <16 x float>, align 16
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72 %0 = load <16 x float>* @T3_retval, align 16
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73 store <16 x float> %0, <16 x float>* %retval
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74 %1 = load <16 x float>* %retval
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75 store <16 x float> %1, <16 x float>* %agg.result, align 16
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76 ret void
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77 }