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annotate lib/Target/AMDGPU/SIDefines.h @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 /// \file
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9 //===----------------------------------------------------------------------===//
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10
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11 #include "llvm/MC/MCInstrDesc.h"
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12
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13 #ifndef LLVM_LIB_TARGET_R600_SIDEFINES_H
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14 #define LLVM_LIB_TARGET_R600_SIDEFINES_H
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15
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16 namespace SIInstrFlags {
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17 // This needs to be kept in sync with the field bits in InstSI.
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18 enum {
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19 SALU = 1 << 3,
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20 VALU = 1 << 4,
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21
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22 SOP1 = 1 << 5,
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23 SOP2 = 1 << 6,
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24 SOPC = 1 << 7,
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25 SOPK = 1 << 8,
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26 SOPP = 1 << 9,
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27
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28 VOP1 = 1 << 10,
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29 VOP2 = 1 << 11,
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30 VOP3 = 1 << 12,
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31 VOPC = 1 << 13,
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32
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33 MUBUF = 1 << 14,
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34 MTBUF = 1 << 15,
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35 SMRD = 1 << 16,
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36 DS = 1 << 17,
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37 MIMG = 1 << 18,
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38 FLAT = 1 << 19,
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39 WQM = 1 << 20,
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40 VGPRSpill = 1 << 21,
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41 VOPAsmPrefer32Bit = 1 << 22
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42 };
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43 }
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44
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45 namespace llvm {
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46 namespace AMDGPU {
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47 enum OperandType {
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48 /// Operand with register or 32-bit immediate
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49 OPERAND_REG_IMM32 = llvm::MCOI::OPERAND_FIRST_TARGET,
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50 /// Operand with register or inline constant
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51 OPERAND_REG_INLINE_C
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52 };
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53 }
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54 }
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55
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56 namespace SIInstrFlags {
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57 enum Flags {
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58 // First 4 bits are the instruction encoding
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59 VM_CNT = 1 << 0,
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60 EXP_CNT = 1 << 1,
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61 LGKM_CNT = 1 << 2
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62 };
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63
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64 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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65 // The result is true if any of these tests are true.
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66 enum ClassFlags {
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67 S_NAN = 1 << 0, // Signaling NaN
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68 Q_NAN = 1 << 1, // Quiet NaN
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69 N_INFINITY = 1 << 2, // Negative infinity
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70 N_NORMAL = 1 << 3, // Negative normal
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71 N_SUBNORMAL = 1 << 4, // Negative subnormal
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72 N_ZERO = 1 << 5, // Negative zero
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73 P_ZERO = 1 << 6, // Positive zero
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74 P_SUBNORMAL = 1 << 7, // Positive subnormal
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75 P_NORMAL = 1 << 8, // Positive normal
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76 P_INFINITY = 1 << 9 // Positive infinity
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77 };
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78 }
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79
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80 namespace SISrcMods {
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81 enum {
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82 NEG = 1 << 0,
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83 ABS = 1 << 1
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84 };
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85 }
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86
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87 namespace SIOutMods {
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88 enum {
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89 NONE = 0,
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90 MUL2 = 1,
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91 MUL4 = 2,
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92 DIV2 = 3
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93 };
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94 }
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95
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96 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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97 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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98 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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99 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
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100 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
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101 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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102 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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103 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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104
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105 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
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106 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
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107 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
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108 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
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109 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
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110 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
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111 #define C_00B84C_USER_SGPR 0xFFFFFFC1
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112 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
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113 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
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114 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
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115 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
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116 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
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117 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
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118 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
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119 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
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120 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
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121 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
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122 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
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123 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
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124 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
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125 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
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126 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
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127 /* CIK */
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128 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
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129 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
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130 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
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131 /* */
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132 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
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133 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
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134 #define C_00B84C_LDS_SIZE 0xFF007FFF
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135 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
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136 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
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137 #define C_00B84C_EXCP_EN
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138
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139 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
100
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140 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
95
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141
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142 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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143 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
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144 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
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145 #define C_00B848_VGPRS 0xFFFFFFC0
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146 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
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147 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
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148 #define C_00B848_SGPRS 0xFFFFFC3F
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149 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
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150 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
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151 #define C_00B848_PRIORITY 0xFFFFF3FF
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152 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
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153 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
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154 #define C_00B848_FLOAT_MODE 0xFFF00FFF
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155 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
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156 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
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157 #define C_00B848_PRIV 0xFFEFFFFF
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158 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
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159 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
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160 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
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161 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
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162 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
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163 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
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164 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
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165 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
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166 #define C_00B848_IEEE_MODE 0xFF7FFFFF
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167
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168
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169 // Helpers for setting FLOAT_MODE
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170 #define FP_ROUND_ROUND_TO_NEAREST 0
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171 #define FP_ROUND_ROUND_TO_INF 1
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172 #define FP_ROUND_ROUND_TO_NEGINF 2
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173 #define FP_ROUND_ROUND_TO_ZERO 3
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174
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175 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
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176 // precision.
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177 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
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178 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
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179
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180 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
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181 #define FP_DENORM_FLUSH_OUT 1
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182 #define FP_DENORM_FLUSH_IN 2
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183 #define FP_DENORM_FLUSH_NONE 3
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184
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185
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186 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
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187 // precision.
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188 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
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189 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
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190
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191 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
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192 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
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193
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194 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
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195 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
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196
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197
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198 #endif