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1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9
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10 #include "PPCTargetTransformInfo.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 #include "llvm/Analysis/TargetTransformInfo.h"
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83
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12 #include "llvm/CodeGen/BasicTTIImpl.h"
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77
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13 #include "llvm/Support/CommandLine.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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14 #include "llvm/Support/Debug.h"
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15 #include "llvm/Target/CostTable.h"
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16 #include "llvm/Target/TargetLowering.h"
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 using namespace llvm;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18
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19 #define DEBUG_TYPE "ppctti"
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20
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21 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
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22 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
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23
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100
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24 // This is currently only used for the data prefetch pass which is only enabled
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25 // for BG/Q by default.
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26 static cl::opt<unsigned>
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27 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
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28 cl::desc("The loop prefetch cache line size"));
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29
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30 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 // PPC cost model.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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34 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35
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83
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36 TargetTransformInfo::PopcntSupportKind
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37 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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38 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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39 if (ST->hasPOPCNTD() && TyWidth <= 64)
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40 return TTI::PSK_FastHardware;
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41 return TTI::PSK_Software;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43
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44 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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45 if (DisablePPCConstHoist)
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46 return BaseT::getIntImmCost(Imm, Ty);
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47
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48 assert(Ty->isIntegerTy());
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49
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50 unsigned BitSize = Ty->getPrimitiveSizeInBits();
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51 if (BitSize == 0)
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52 return ~0U;
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53
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54 if (Imm == 0)
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55 return TTI::TCC_Free;
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56
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57 if (Imm.getBitWidth() <= 64) {
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58 if (isInt<16>(Imm.getSExtValue()))
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59 return TTI::TCC_Basic;
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60
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61 if (isInt<32>(Imm.getSExtValue())) {
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62 // A constant that can be materialized using lis.
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63 if ((Imm.getZExtValue() & 0xFFFF) == 0)
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64 return TTI::TCC_Basic;
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65
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66 return 2 * TTI::TCC_Basic;
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77
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67 }
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68 }
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69
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70 return 4 * TTI::TCC_Basic;
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77
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71 }
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72
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73 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
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74 Type *Ty) {
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75 if (DisablePPCConstHoist)
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76 return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
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77
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77
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78 assert(Ty->isIntegerTy());
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79
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80 unsigned BitSize = Ty->getPrimitiveSizeInBits();
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81 if (BitSize == 0)
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82 return ~0U;
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83
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84 switch (IID) {
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83
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85 default:
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86 return TTI::TCC_Free;
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77
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87 case Intrinsic::sadd_with_overflow:
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88 case Intrinsic::uadd_with_overflow:
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89 case Intrinsic::ssub_with_overflow:
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90 case Intrinsic::usub_with_overflow:
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91 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
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92 return TTI::TCC_Free;
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93 break;
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94 case Intrinsic::experimental_stackmap:
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95 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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96 return TTI::TCC_Free;
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97 break;
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98 case Intrinsic::experimental_patchpoint_void:
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99 case Intrinsic::experimental_patchpoint_i64:
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100 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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101 return TTI::TCC_Free;
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102 break;
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103 }
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104 return PPCTTIImpl::getIntImmCost(Imm, Ty);
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105 }
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106
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107 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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108 Type *Ty) {
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109 if (DisablePPCConstHoist)
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110 return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty);
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111
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112 assert(Ty->isIntegerTy());
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113
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114 unsigned BitSize = Ty->getPrimitiveSizeInBits();
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115 if (BitSize == 0)
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116 return ~0U;
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117
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118 unsigned ImmIdx = ~0U;
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119 bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
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120 ZeroFree = false;
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121 switch (Opcode) {
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122 default:
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123 return TTI::TCC_Free;
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124 case Instruction::GetElementPtr:
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125 // Always hoist the base address of a GetElementPtr. This prevents the
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126 // creation of new constants for every base constant that gets constant
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127 // folded with the offset.
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128 if (Idx == 0)
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129 return 2 * TTI::TCC_Basic;
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130 return TTI::TCC_Free;
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131 case Instruction::And:
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132 RunFree = true; // (for the rotate-and-mask instructions)
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133 // Fallthrough...
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134 case Instruction::Add:
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135 case Instruction::Or:
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136 case Instruction::Xor:
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137 ShiftedFree = true;
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138 // Fallthrough...
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139 case Instruction::Sub:
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140 case Instruction::Mul:
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141 case Instruction::Shl:
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142 case Instruction::LShr:
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143 case Instruction::AShr:
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144 ImmIdx = 1;
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145 break;
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146 case Instruction::ICmp:
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147 UnsignedFree = true;
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148 ImmIdx = 1;
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149 // Fallthrough... (zero comparisons can use record-form instructions)
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150 case Instruction::Select:
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151 ZeroFree = true;
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152 break;
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153 case Instruction::PHI:
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154 case Instruction::Call:
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155 case Instruction::Ret:
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156 case Instruction::Load:
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157 case Instruction::Store:
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158 break;
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159 }
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160
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161 if (ZeroFree && Imm == 0)
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162 return TTI::TCC_Free;
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163
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164 if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
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165 if (isInt<16>(Imm.getSExtValue()))
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166 return TTI::TCC_Free;
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167
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168 if (RunFree) {
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169 if (Imm.getBitWidth() <= 32 &&
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170 (isShiftedMask_32(Imm.getZExtValue()) ||
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171 isShiftedMask_32(~Imm.getZExtValue())))
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172 return TTI::TCC_Free;
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173
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174 if (ST->isPPC64() &&
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175 (isShiftedMask_64(Imm.getZExtValue()) ||
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176 isShiftedMask_64(~Imm.getZExtValue())))
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177 return TTI::TCC_Free;
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178 }
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179
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180 if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
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181 return TTI::TCC_Free;
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182
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183 if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
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184 return TTI::TCC_Free;
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185 }
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186
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187 return PPCTTIImpl::getIntImmCost(Imm, Ty);
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188 }
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189
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190 void PPCTTIImpl::getUnrollingPreferences(Loop *L,
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191 TTI::UnrollingPreferences &UP) {
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192 if (ST->getDarwinDirective() == PPC::DIR_A2) {
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193 // The A2 is in-order with a deep pipeline, and concatenation unrolling
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194 // helps expose latency-hiding opportunities to the instruction scheduler.
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195 UP.Partial = UP.Runtime = true;
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196
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197 // We unroll a lot on the A2 (hundreds of instructions), and the benefits
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198 // often outweigh the cost of a division to compute the trip count.
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199 UP.AllowExpensiveTripCount = true;
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200 }
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201
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202 BaseT::getUnrollingPreferences(L, UP);
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203 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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204
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205 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
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206 // On the A2, always unroll aggressively. For QPX unaligned loads, we depend
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207 // on combining the loads generated for consecutive accesses, and failure to
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208 // do so is particularly expensive. This makes it much more likely (compared
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209 // to only using concatenation unrolling).
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210 if (ST->getDarwinDirective() == PPC::DIR_A2)
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211 return true;
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212
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213 return LoopHasReductions;
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214 }
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215
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216 bool PPCTTIImpl::enableInterleavedAccessVectorization() {
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217 return true;
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218 }
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219
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220 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
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221 if (Vector && !ST->hasAltivec() && !ST->hasQPX())
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222 return 0;
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223 return ST->hasVSX() ? 64 : 32;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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224 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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225
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226 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) {
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227 if (Vector) {
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228 if (ST->hasQPX()) return 256;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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229 if (ST->hasAltivec()) return 128;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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230 return 0;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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231 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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232
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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233 if (ST->isPPC64())
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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234 return 64;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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235 return 32;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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236
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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237 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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238
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100
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239 unsigned PPCTTIImpl::getCacheLineSize() {
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240 // This is currently only used for the data prefetch pass which is only
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241 // enabled for BG/Q by default.
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242 return CacheLineSize;
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243 }
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244
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95
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245 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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246 unsigned Directive = ST->getDarwinDirective();
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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247 // The 440 has no SIMD support, but floating-point instructions
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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248 // have a 5-cycle latency, so unroll by 5x for latency hiding.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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249 if (Directive == PPC::DIR_440)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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250 return 5;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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251
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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252 // The A2 has no SIMD support, but floating-point instructions
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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253 // have a 6-cycle latency, so unroll by 6x for latency hiding.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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254 if (Directive == PPC::DIR_A2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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255 return 6;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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256
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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257 // FIXME: For lack of any better information, do no harm...
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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258 if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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259 return 1;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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260
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83
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261 // For P7 and P8, floating-point instructions have a 6-cycle latency and
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262 // there are two execution units, so unroll by 12x for latency hiding.
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263 if (Directive == PPC::DIR_PWR7 ||
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264 Directive == PPC::DIR_PWR8)
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265 return 12;
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266
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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267 // For most things, modern systems have two execution units (and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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268 // out-of-order execution).
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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269 return 2;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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270 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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271
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95
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272 int PPCTTIImpl::getArithmeticInstrCost(
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83
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273 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
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274 TTI::OperandValueKind Op2Info, TTI::OperandValueProperties Opd1PropInfo,
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275 TTI::OperandValueProperties Opd2PropInfo) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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276 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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277
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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278 // Fallback to the default implementation.
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83
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279 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
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280 Opd1PropInfo, Opd2PropInfo);
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281 }
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282
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95
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283 int PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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284 Type *SubTp) {
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285 // Legalize the type.
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286 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
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287
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288 // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
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289 // (at least in the sense that there need only be one non-loop-invariant
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290 // instruction). We need one such shuffle instruction for each actual
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291 // register (this is not true for arbitrary shuffles, but is true for the
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292 // structured types of shuffles covered by TTI::ShuffleKind).
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293 return LT.first;
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294 }
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295
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95
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296 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
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297 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
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298
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83
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299 return BaseT::getCastInstrCost(Opcode, Dst, Src);
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300 }
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301
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95
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302 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
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83
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303 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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304 }
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305
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95
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306 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
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307 assert(Val->isVectorTy() && "This must be a vector type");
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308
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309 int ISD = TLI->InstructionOpcodeToISD(Opcode);
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310 assert(ISD && "Invalid opcode");
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311
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312 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
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313 // Double-precision scalars are already located in index #0.
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314 if (Index == 0)
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315 return 0;
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316
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83
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317 return BaseT::getVectorInstrCost(Opcode, Val, Index);
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95
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318 } else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) {
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319 // Floating point scalars are already located in index #0.
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320 if (Index == 0)
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321 return 0;
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322
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323 return BaseT::getVectorInstrCost(Opcode, Val, Index);
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77
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324 }
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325
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326 // Estimated cost of a load-hit-store delay. This was obtained
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327 // experimentally as a minimum needed to prevent unprofitable
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328 // vectorization for the paq8p benchmark. It may need to be
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329 // raised further if other unprofitable cases remain.
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77
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330 unsigned LHSPenalty = 2;
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331 if (ISD == ISD::INSERT_VECTOR_ELT)
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332 LHSPenalty += 7;
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333
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334 // Vector element insert/extract with Altivec is very expensive,
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335 // because they require store and reload with the attendant
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336 // processor stall for load-hit-store. Until VSX is available,
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337 // these need to be estimated as very costly.
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338 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
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339 ISD == ISD::INSERT_VECTOR_ELT)
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83
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340 return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index);
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341
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83
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342 return BaseT::getVectorInstrCost(Opcode, Val, Index);
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343 }
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344
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95
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345 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
|
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346 unsigned AddressSpace) {
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347 // Legalize the type.
|
|
95
|
348 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
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349 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
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|
350 "Invalid Opcode");
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351
|
|
95
|
352 int Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
|
|
|
353
|
|
|
354 // Aligned loads and stores are easy.
|
|
|
355 unsigned SrcBytes = LT.second.getStoreSize();
|
|
|
356 if (!SrcBytes || !Alignment || Alignment >= SrcBytes)
|
|
|
357 return Cost;
|
|
|
358
|
|
|
359 bool IsAltivecType = ST->hasAltivec() &&
|
|
|
360 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
|
|
|
361 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
|
|
|
362 bool IsVSXType = ST->hasVSX() &&
|
|
|
363 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
|
|
|
364 bool IsQPXType = ST->hasQPX() &&
|
|
|
365 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
|
|
77
|
366
|
|
95
|
367 // If we can use the permutation-based load sequence, then this is also
|
|
|
368 // relatively cheap (not counting loop-invariant instructions): one load plus
|
|
|
369 // one permute (the last load in a series has extra cost, but we're
|
|
|
370 // neglecting that here). Note that on the P7, we should do unaligned loads
|
|
|
371 // for Altivec types using the VSX instructions, but that's more expensive
|
|
|
372 // than using the permutation-based load sequence. On the P8, that's no
|
|
|
373 // longer true.
|
|
|
374 if (Opcode == Instruction::Load &&
|
|
|
375 ((!ST->hasP8Vector() && IsAltivecType) || IsQPXType) &&
|
|
|
376 Alignment >= LT.second.getScalarType().getStoreSize())
|
|
|
377 return Cost + LT.first; // Add the cost of the permutations.
|
|
77
|
378
|
|
95
|
379 // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the
|
|
|
380 // P7, unaligned vector loads are more expensive than the permutation-based
|
|
|
381 // load sequence, so that might be used instead, but regardless, the net cost
|
|
|
382 // is about the same (not counting loop-invariant instructions).
|
|
|
383 if (IsVSXType || (ST->hasVSX() && IsAltivecType))
|
|
|
384 return Cost;
|
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|
385
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
386 // PPC in general does not support unaligned loads and stores. They'll need
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
387 // to be decomposed based on the alignment factor.
|
|
95
|
388
|
|
|
389 // Add the cost of each scalar load or store.
|
|
|
390 Cost += LT.first*(SrcBytes/Alignment-1);
|
|
77
|
391
|
|
95
|
392 // For a vector type, there is also scalarization overhead (only for
|
|
|
393 // stores, loads are expanded using the vector-load + permutation sequence,
|
|
|
394 // which is much less expensive).
|
|
|
395 if (Src->isVectorTy() && Opcode == Instruction::Store)
|
|
|
396 for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
|
|
|
397 Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
|
0
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parents:
diff
changeset
|
398
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
399 return Cost;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
400 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
401
|
|
95
|
402 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
|
|
|
403 unsigned Factor,
|
|
|
404 ArrayRef<unsigned> Indices,
|
|
|
405 unsigned Alignment,
|
|
|
406 unsigned AddressSpace) {
|
|
|
407 assert(isa<VectorType>(VecTy) &&
|
|
|
408 "Expect a vector type for interleaved memory op");
|
|
|
409
|
|
|
410 // Legalize the type.
|
|
|
411 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy);
|
|
|
412
|
|
|
413 // Firstly, the cost of load/store operation.
|
|
|
414 int Cost = getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace);
|
|
|
415
|
|
|
416 // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
|
|
|
417 // (at least in the sense that there need only be one non-loop-invariant
|
|
|
418 // instruction). For each result vector, we need one shuffle per incoming
|
|
|
419 // vector (except that the first shuffle can take two incoming vectors
|
|
|
420 // because it does not need to take itself).
|
|
|
421 Cost += Factor*(LT.first-1);
|
|
|
422
|
|
|
423 return Cost;
|
|
|
424 }
|
|
|
425
|
