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annotate test/CodeGen/ARM/fp16-v3.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
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children 1172e4bd9c6f
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100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK
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2
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3 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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4 target triple = "armv7a--none-eabi"
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5
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6 ; CHECK-LABEL: test_vec3:
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7 ; CHECK: vcvtb.f32.f16
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8 ; CHECK: vcvt.f32.s32
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9 ; CHECK: vadd.f32
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10 ; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}}
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11 ; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]]
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12 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
7d135dc70f03 LLVM 3.9
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13 ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16
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14 ; CHECK-DAG: strh [[RREG1]], [r0, #4]
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15 ; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
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16 ; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
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17 ; CHECK-NEXT: bx lr
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18 define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
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19 %H = sitofp i32 %i to half
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20 %S = fadd half %H, 0xH4A00
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21 %1 = insertelement <3 x half> undef, half %S, i32 0
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22 %2 = insertelement <3 x half> %1, half %S, i32 1
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23 %3 = insertelement <3 x half> %2, half %S, i32 2
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24 store <3 x half> %3, <3 x half>* %arr, align 8
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25 ret void
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26 }
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27
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28 attributes #0 = { nounwind }