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annotate test/CodeGen/Mips/inlineasm-operand-code.ll @ 100:7d135dc70f03

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1 ; Positive test for inline register constraints
95c75e76d11b LLVM 3.4
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parents:
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2 ;
100
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parents: 95
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3 ; RUN: llc -no-integrated-as -march=mipsel < %s | \
7d135dc70f03 LLVM 3.9
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parents: 95
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4 ; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s
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parents: 95
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5 ; RUN: llc -no-integrated-as -march=mips < %s | \
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parents: 95
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6 ; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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7
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parents:
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8 %union.u_tag = type { i64 }
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parents:
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9 %struct.anon = type { i32, i32 }
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parents:
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10 @uval = common global %union.u_tag zeroinitializer, align 8
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parents:
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11
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parents:
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12 ; X with -3
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parents:
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13 define i32 @constraint_X() nounwind {
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parents:
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14 entry:
100
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parents: 95
diff changeset
15 ; ALL-LABEL: constraint_X:
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parents: 95
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16 ; ALL: #APP
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parents: 95
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17 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
7d135dc70f03 LLVM 3.9
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parents: 95
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18 ; ALL: #NO_APP
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parents: 95
diff changeset
19 tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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20 ret i32 0
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parents:
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21 }
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parents:
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22
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parents:
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23 ; x with -3
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parents:
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24 define i32 @constraint_x() nounwind {
95c75e76d11b LLVM 3.4
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parents:
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25 entry:
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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26 ; ALL-LABEL: constraint_x:
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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27 ; ALL: #APP
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parents: 95
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28 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
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parents: 95
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29 ; ALL: #NO_APP
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parents: 95
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30 tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
0
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parents:
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31 ret i32 0
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parents:
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32 }
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parents:
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33
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parents:
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34 ; d with -3
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parents:
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35 define i32 @constraint_d() nounwind {
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parents:
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36 entry:
100
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parents: 95
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37 ; ALL-LABEL: constraint_d:
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parents: 95
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38 ; ALL: #APP
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parents: 95
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39 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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40 ; ALL: #NO_APP
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parents: 95
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41 tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 ret i32 0
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parents:
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43 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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44
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 ; m with -3
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 define i32 @constraint_m() nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 entry:
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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48 ; ALL-LABEL: constraint_m:
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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49 ; ALL: #APP
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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50 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
51 ; ALL: #NO_APP
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
52 tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
53 ret i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 ; z with -3
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
57 define i32 @constraint_z() nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58 entry:
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
59 ; ALL-LABEL: constraint_z:
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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60 ; ALL: #APP
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parents: 95
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61 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
62 ; ALL: #NO_APP
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parents: 95
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63 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
64
95c75e76d11b LLVM 3.4
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parents:
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65 ; z with 0
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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66 ; ALL: #APP
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parents: 95
diff changeset
67 ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
68 ; ALL: #NO_APP
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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69 tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
70
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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71 ; z with non-zero and the "r"(register) and "J"(integer zero) constraints
100
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parents: 95
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72 ; ALL: #APP
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parents: 95
diff changeset
73 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
74 ; ALL: #NO_APP
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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75 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
76
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
77 ; z with zero and the "r"(register) and "J"(integer zero) constraints
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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78 ; ALL: #APP
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parents: 95
diff changeset
79 ; ALL: mtc0 $0, ${{[0-9]+}}
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parents: 95
diff changeset
80 ; ALL: #NO_APP
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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81 call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
82
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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83 ; z with non-zero and just the "r"(register) constraint
100
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parents: 95
diff changeset
84 ; ALL: #APP
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parents: 95
diff changeset
85 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
86 ; ALL: #NO_APP
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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87 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
88
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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89 ; z with zero and just the "r"(register) constraint
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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90 ; FIXME: Check for $0, instead of other registers.
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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91 ; We should be using $0 directly in this case, not real registers.
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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92 ; When the materialization of 0 gets fixed, this test will fail.
100
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parents: 95
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93 ; ALL: #APP
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parents: 95
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94 ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
95 ; ALL: #NO_APP
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
96 call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
0
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parents:
diff changeset
97 ret i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
98 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
99
100
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parents: 95
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100 ; A long long in 32 bit mode (use to assert)
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
101 define i32 @constraint_longlong() nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
102 entry:
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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103 ; ALL-LABEL: constraint_longlong:
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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104 ; ALL: #APP
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
105 ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
106 ; ALL: #NO_APP
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parents: 95
diff changeset
107 tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
108 ret i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
109 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
110
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
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111 ; In little endian the source reg will be 4 bytes into the long long
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
112 ; In big endian the source reg will also be 4 bytes into the long long
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
113 define i32 @constraint_D() nounwind {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114 entry:
100
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
115 ; ALL-LABEL: constraint_D:
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
116 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
117 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
118 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
119 ; ALL: #APP
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
120 ; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
121 ; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
122 ; ALL: #NO_APP
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
123 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
124 %trunc1 = trunc i64 %bosco to i32
100
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parents: 95
diff changeset
125 tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 ret i32 0
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parents:
diff changeset
127 }
95c75e76d11b LLVM 3.4
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parents:
diff changeset
128
100
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parents: 95
diff changeset
129 ; In little endian the source reg will be 0 bytes into the long long
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parents: 95
diff changeset
130 ; In big endian the source reg will be 4 bytes into the long long
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 define i32 @constraint_L() nounwind {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 entry:
100
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parents: 95
diff changeset
133 ; ALL-LABEL: constraint_L:
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parents: 95
diff changeset
134 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
135 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
7d135dc70f03 LLVM 3.9
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parents: 95
diff changeset
136 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
7d135dc70f03 LLVM 3.9
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parents: 95
diff changeset
137 ; ALL: #APP
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
138 ; LE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
139 ; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
140 ; ALL: #NO_APP
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
141 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 %trunc1 = trunc i64 %bosco to i32
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
143 tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 ret i32 0
95c75e76d11b LLVM 3.4
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parents:
diff changeset
145 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146
100
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parents: 95
diff changeset
147 ; In little endian the source reg will be 4 bytes into the long long
7d135dc70f03 LLVM 3.9
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parents: 95
diff changeset
148 ; In big endian the source reg will be 0 bytes into the long long
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 define i32 @constraint_M() nounwind {
95c75e76d11b LLVM 3.4
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parents:
diff changeset
150 entry:
100
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parents: 95
diff changeset
151 ; ALL-LABEL: constraint_M:
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parents: 95
diff changeset
152 ; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
153 ; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
154 ; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
155 ; ALL: #APP
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
156 ; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
157 ; BE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
158 ; ALL: #NO_APP
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
159 %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 %trunc1 = trunc i64 %bosco to i32
100
7d135dc70f03 LLVM 3.9
Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
parents: 95
diff changeset
161 tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 ret i32 0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 }