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121
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1 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
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2 ---
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3 # GCN-LABEL: name: v_max_self_clamp_not_set_f32
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4 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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5 # GCN-NEXT: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
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6
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7 name: v_max_self_clamp_not_set_f32
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8 tracksRegLiveness: true
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9 registers:
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10 - { id: 0, class: sgpr_64 }
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11 - { id: 1, class: sreg_32_xm0 }
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12 - { id: 2, class: sgpr_32 }
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13 - { id: 3, class: vgpr_32 }
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14 - { id: 4, class: sreg_64_xexec }
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15 - { id: 5, class: sreg_64_xexec }
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16 - { id: 6, class: sreg_32 }
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17 - { id: 7, class: sreg_32 }
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18 - { id: 8, class: sreg_32_xm0 }
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19 - { id: 9, class: sreg_64 }
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20 - { id: 10, class: sreg_32_xm0 }
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21 - { id: 11, class: sreg_32_xm0 }
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22 - { id: 12, class: sgpr_64 }
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23 - { id: 13, class: sgpr_128 }
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24 - { id: 14, class: sreg_32_xm0 }
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25 - { id: 15, class: sreg_64 }
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26 - { id: 16, class: sgpr_128 }
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27 - { id: 17, class: vgpr_32 }
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28 - { id: 18, class: vreg_64 }
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29 - { id: 19, class: vgpr_32 }
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30 - { id: 20, class: vgpr_32 }
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31 - { id: 21, class: vgpr_32 }
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32 - { id: 22, class: vgpr_32 }
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33 - { id: 23, class: vreg_64 }
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34 - { id: 24, class: vgpr_32 }
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35 - { id: 25, class: vreg_64 }
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36 - { id: 26, class: vreg_64 }
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37 liveins:
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38 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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39 - { reg: '%vgpr0', virtual-reg: '%3' }
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40 body: |
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41 bb.0:
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42 liveins: %sgpr0_sgpr1, %vgpr0
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43
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44 %3 = COPY %vgpr0
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45 %0 = COPY %sgpr0_sgpr1
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46 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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47 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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48 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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49 %25 = REG_SEQUENCE %3, 1, %24, 2
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50 %10 = S_MOV_B32 61440
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51 %11 = S_MOV_B32 0
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52 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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53 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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54 %14 = S_MOV_B32 2
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55 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
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56 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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57 %18 = COPY %26
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58 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
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59 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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60 %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit %exec
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61 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
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62 S_ENDPGM
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63
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64 ...
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65 ---
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66 # GCN-LABEL: name: v_clamp_omod_already_set_f32
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67 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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68 # GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
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69 name: v_clamp_omod_already_set_f32
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70 tracksRegLiveness: true
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71 registers:
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72 - { id: 0, class: sgpr_64 }
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73 - { id: 1, class: sreg_32_xm0 }
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74 - { id: 2, class: sgpr_32 }
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75 - { id: 3, class: vgpr_32 }
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76 - { id: 4, class: sreg_64_xexec }
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77 - { id: 5, class: sreg_64_xexec }
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78 - { id: 6, class: sreg_32 }
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79 - { id: 7, class: sreg_32 }
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80 - { id: 8, class: sreg_32_xm0 }
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81 - { id: 9, class: sreg_64 }
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82 - { id: 10, class: sreg_32_xm0 }
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83 - { id: 11, class: sreg_32_xm0 }
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84 - { id: 12, class: sgpr_64 }
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85 - { id: 13, class: sgpr_128 }
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86 - { id: 14, class: sreg_32_xm0 }
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87 - { id: 15, class: sreg_64 }
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88 - { id: 16, class: sgpr_128 }
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89 - { id: 17, class: vgpr_32 }
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90 - { id: 18, class: vreg_64 }
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91 - { id: 19, class: vgpr_32 }
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92 - { id: 20, class: vgpr_32 }
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93 - { id: 21, class: vgpr_32 }
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94 - { id: 22, class: vgpr_32 }
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95 - { id: 23, class: vreg_64 }
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96 - { id: 24, class: vgpr_32 }
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97 - { id: 25, class: vreg_64 }
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98 - { id: 26, class: vreg_64 }
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99 liveins:
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100 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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101 - { reg: '%vgpr0', virtual-reg: '%3' }
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102 body: |
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103 bb.0:
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104 liveins: %sgpr0_sgpr1, %vgpr0
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105
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106 %3 = COPY %vgpr0
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107 %0 = COPY %sgpr0_sgpr1
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108 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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109 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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110 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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111 %25 = REG_SEQUENCE %3, 1, %24, 2
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112 %10 = S_MOV_B32 61440
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113 %11 = S_MOV_B32 0
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114 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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115 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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116 %14 = S_MOV_B32 2
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117 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
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118 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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119 %18 = COPY %26
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120 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
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121 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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122 %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit %exec
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123 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
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124 S_ENDPGM
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125 ...
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126 ---
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127 # Don't fold a mul that looks like an omod if itself has omod set
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128
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129 # GCN-LABEL: name: v_omod_mul_omod_already_set_f32
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130 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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131 # GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit %exec
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132 name: v_omod_mul_omod_already_set_f32
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133 tracksRegLiveness: true
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134 registers:
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135 - { id: 0, class: sgpr_64 }
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136 - { id: 1, class: sreg_32_xm0 }
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137 - { id: 2, class: sgpr_32 }
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138 - { id: 3, class: vgpr_32 }
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139 - { id: 4, class: sreg_64_xexec }
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140 - { id: 5, class: sreg_64_xexec }
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141 - { id: 6, class: sreg_32 }
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142 - { id: 7, class: sreg_32 }
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143 - { id: 8, class: sreg_32_xm0 }
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144 - { id: 9, class: sreg_64 }
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145 - { id: 10, class: sreg_32_xm0 }
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146 - { id: 11, class: sreg_32_xm0 }
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147 - { id: 12, class: sgpr_64 }
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148 - { id: 13, class: sgpr_128 }
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149 - { id: 14, class: sreg_32_xm0 }
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150 - { id: 15, class: sreg_64 }
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151 - { id: 16, class: sgpr_128 }
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152 - { id: 17, class: vgpr_32 }
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153 - { id: 18, class: vreg_64 }
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154 - { id: 19, class: vgpr_32 }
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155 - { id: 20, class: vgpr_32 }
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156 - { id: 21, class: vgpr_32 }
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157 - { id: 22, class: vgpr_32 }
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158 - { id: 23, class: vreg_64 }
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159 - { id: 24, class: vgpr_32 }
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160 - { id: 25, class: vreg_64 }
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161 - { id: 26, class: vreg_64 }
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162 liveins:
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163 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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164 - { reg: '%vgpr0', virtual-reg: '%3' }
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165 body: |
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166 bb.0:
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167 liveins: %sgpr0_sgpr1, %vgpr0
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168
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169 %3 = COPY %vgpr0
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170 %0 = COPY %sgpr0_sgpr1
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171 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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172 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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173 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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174 %25 = REG_SEQUENCE %3, 1, %24, 2
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175 %10 = S_MOV_B32 61440
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176 %11 = S_MOV_B32 0
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177 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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178 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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179 %14 = S_MOV_B32 2
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180 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
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181 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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182 %18 = COPY %26
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183 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
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184 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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185 %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit %exec
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186 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
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187 S_ENDPGM
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188
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189 ...
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190 ---
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191 # Don't fold a mul that looks like an omod if itself has clamp set
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192 # This might be OK, but would require folding the clamp at the same time.
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193 # GCN-LABEL: name: v_omod_mul_clamp_already_set_f32
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194 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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195 # GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit %exec
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196
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197 name: v_omod_mul_clamp_already_set_f32
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198 tracksRegLiveness: true
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199 registers:
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200 - { id: 0, class: sgpr_64 }
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201 - { id: 1, class: sreg_32_xm0 }
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202 - { id: 2, class: sgpr_32 }
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203 - { id: 3, class: vgpr_32 }
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204 - { id: 4, class: sreg_64_xexec }
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205 - { id: 5, class: sreg_64_xexec }
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206 - { id: 6, class: sreg_32 }
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207 - { id: 7, class: sreg_32 }
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208 - { id: 8, class: sreg_32_xm0 }
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209 - { id: 9, class: sreg_64 }
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210 - { id: 10, class: sreg_32_xm0 }
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211 - { id: 11, class: sreg_32_xm0 }
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212 - { id: 12, class: sgpr_64 }
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213 - { id: 13, class: sgpr_128 }
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214 - { id: 14, class: sreg_32_xm0 }
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215 - { id: 15, class: sreg_64 }
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216 - { id: 16, class: sgpr_128 }
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217 - { id: 17, class: vgpr_32 }
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218 - { id: 18, class: vreg_64 }
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219 - { id: 19, class: vgpr_32 }
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220 - { id: 20, class: vgpr_32 }
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221 - { id: 21, class: vgpr_32 }
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222 - { id: 22, class: vgpr_32 }
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223 - { id: 23, class: vreg_64 }
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224 - { id: 24, class: vgpr_32 }
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225 - { id: 25, class: vreg_64 }
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226 - { id: 26, class: vreg_64 }
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227 liveins:
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228 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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229 - { reg: '%vgpr0', virtual-reg: '%3' }
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230 body: |
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231 bb.0:
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232 liveins: %sgpr0_sgpr1, %vgpr0
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233
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234 %3 = COPY %vgpr0
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235 %0 = COPY %sgpr0_sgpr1
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236 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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237 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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238 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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239 %25 = REG_SEQUENCE %3, 1, %24, 2
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240 %10 = S_MOV_B32 61440
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241 %11 = S_MOV_B32 0
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242 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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243 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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244 %14 = S_MOV_B32 2
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245 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
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246 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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247 %18 = COPY %26
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248 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
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249 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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250 %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit %exec
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251 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
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252 S_ENDPGM
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253
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254 ...
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255
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256
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257
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258
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259
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260
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261
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262
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263
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264
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265
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266
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267
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268 ---
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269 # Don't fold a mul that looks like an omod if itself has omod set
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270
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271 # GCN-LABEL: name: v_omod_add_omod_already_set_f32
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272 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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273 # GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit %exec
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274 name: v_omod_add_omod_already_set_f32
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275 tracksRegLiveness: true
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276 registers:
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277 - { id: 0, class: sgpr_64 }
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278 - { id: 1, class: sreg_32_xm0 }
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279 - { id: 2, class: sgpr_32 }
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280 - { id: 3, class: vgpr_32 }
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281 - { id: 4, class: sreg_64_xexec }
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282 - { id: 5, class: sreg_64_xexec }
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283 - { id: 6, class: sreg_32 }
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284 - { id: 7, class: sreg_32 }
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285 - { id: 8, class: sreg_32_xm0 }
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286 - { id: 9, class: sreg_64 }
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287 - { id: 10, class: sreg_32_xm0 }
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288 - { id: 11, class: sreg_32_xm0 }
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289 - { id: 12, class: sgpr_64 }
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290 - { id: 13, class: sgpr_128 }
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291 - { id: 14, class: sreg_32_xm0 }
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292 - { id: 15, class: sreg_64 }
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293 - { id: 16, class: sgpr_128 }
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294 - { id: 17, class: vgpr_32 }
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295 - { id: 18, class: vreg_64 }
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296 - { id: 19, class: vgpr_32 }
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297 - { id: 20, class: vgpr_32 }
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298 - { id: 21, class: vgpr_32 }
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299 - { id: 22, class: vgpr_32 }
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300 - { id: 23, class: vreg_64 }
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301 - { id: 24, class: vgpr_32 }
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302 - { id: 25, class: vreg_64 }
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303 - { id: 26, class: vreg_64 }
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304 liveins:
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305 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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306 - { reg: '%vgpr0', virtual-reg: '%3' }
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307 body: |
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308 bb.0:
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309 liveins: %sgpr0_sgpr1, %vgpr0
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310
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311 %3 = COPY %vgpr0
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312 %0 = COPY %sgpr0_sgpr1
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313 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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314 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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315 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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316 %25 = REG_SEQUENCE %3, 1, %24, 2
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317 %10 = S_MOV_B32 61440
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318 %11 = S_MOV_B32 0
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319 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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320 %13 = REG_SEQUENCE killed %5, 17, %12, 18
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321 %14 = S_MOV_B32 2
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322 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
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323 %16 = REG_SEQUENCE killed %4, 17, %12, 18
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324 %18 = COPY %26
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325 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
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326 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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327 %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit %exec
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328 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
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329 S_ENDPGM
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330
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331 ...
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332 ---
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333 # Don't fold a mul that looks like an omod if itself has clamp set
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334 # This might be OK, but would require folding the clamp at the same time.
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335 # GCN-LABEL: name: v_omod_add_clamp_already_set_f32
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336 # GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
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337 # GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit %exec
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338
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339 name: v_omod_add_clamp_already_set_f32
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340 tracksRegLiveness: true
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341 registers:
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342 - { id: 0, class: sgpr_64 }
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343 - { id: 1, class: sreg_32_xm0 }
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344 - { id: 2, class: sgpr_32 }
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345 - { id: 3, class: vgpr_32 }
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346 - { id: 4, class: sreg_64_xexec }
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347 - { id: 5, class: sreg_64_xexec }
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348 - { id: 6, class: sreg_32 }
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349 - { id: 7, class: sreg_32 }
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350 - { id: 8, class: sreg_32_xm0 }
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351 - { id: 9, class: sreg_64 }
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352 - { id: 10, class: sreg_32_xm0 }
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353 - { id: 11, class: sreg_32_xm0 }
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354 - { id: 12, class: sgpr_64 }
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355 - { id: 13, class: sgpr_128 }
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356 - { id: 14, class: sreg_32_xm0 }
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357 - { id: 15, class: sreg_64 }
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358 - { id: 16, class: sgpr_128 }
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359 - { id: 17, class: vgpr_32 }
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360 - { id: 18, class: vreg_64 }
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361 - { id: 19, class: vgpr_32 }
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362 - { id: 20, class: vgpr_32 }
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|
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363 - { id: 21, class: vgpr_32 }
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|
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364 - { id: 22, class: vgpr_32 }
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|
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365 - { id: 23, class: vreg_64 }
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|
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366 - { id: 24, class: vgpr_32 }
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|
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367 - { id: 25, class: vreg_64 }
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|
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368 - { id: 26, class: vreg_64 }
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|
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369 liveins:
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|
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370 - { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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|
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371 - { reg: '%vgpr0', virtual-reg: '%3' }
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372 body: |
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|
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373 bb.0:
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374 liveins: %sgpr0_sgpr1, %vgpr0
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375
|
|
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376 %3 = COPY %vgpr0
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|
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377 %0 = COPY %sgpr0_sgpr1
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|
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378 %4 = S_LOAD_DWORDX2_IMM %0, 9, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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|
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379 %5 = S_LOAD_DWORDX2_IMM %0, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)
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|
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380 %24 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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|
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381 %25 = REG_SEQUENCE %3, 1, %24, 2
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|
|
382 %10 = S_MOV_B32 61440
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|
|
383 %11 = S_MOV_B32 0
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|
|
384 %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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|
|
385 %13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
|
386 %14 = S_MOV_B32 2
|
|
|
387 %26 = V_LSHL_B64 killed %25, 2, implicit %exec
|
|
|
388 %16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
|
389 %18 = COPY %26
|
|
|
390 %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, implicit %exec
|
|
|
391 %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit %exec
|
|
|
392 %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit %exec
|
|
|
393 BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, implicit %exec
|
|
|
394 S_ENDPGM
|
|
|
395
|
|
|
396 ...
|
|
|
397 ---
|
|
|
398
|
|
|
399 # Pass used to crash with immediate second operand of max
|
|
|
400 name: v_max_reg_imm_f32
|
|
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401 tracksRegLiveness: true
|
|
|
402 registers:
|
|
|
403 - { id: 0, class: vgpr_32 }
|
|
|
404 - { id: 1, class: vgpr_32 }
|
|
|
405 body: |
|
|
|
406 bb.0:
|
|
|
407 liveins: %vgpr0
|
|
|
408
|
|
|
409 %0 = COPY %vgpr0
|
|
|
410 %1 = V_MAX_F32_e64 0, killed %0, 0, 1056964608, 1, 0, implicit %exec
|
|
|
411
|
|
|
412 ...
|
