|
120
|
1 ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
|
|
2
|
|
|
3 ; If the workgroup id range is restricted, we should be able to use
|
|
|
4 ; mad24 for the usual indexing pattern.
|
|
|
5
|
|
|
6 declare i32 @llvm.amdgcn.workgroup.id.x() #0
|
|
|
7 declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
8 declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
|
|
|
9
|
|
|
10 ; GCN-LABEL: {{^}}get_global_id_0:
|
|
|
11 ; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff
|
|
|
12 ; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]]
|
|
121
|
13 ; GCN: v_mad_u32_u24 v{{[0-9]+}}, s8, [[VWGSIZEX]], v0
|
|
|
14 define amdgpu_kernel void @get_global_id_0(i32 addrspace(1)* %out) #1 {
|
|
120
|
15 %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
|
|
|
16 %cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)*
|
|
|
17 %gep = getelementptr inbounds i32, i32 addrspace(2)* %cast.dispatch.ptr, i64 1
|
|
|
18 %workgroup.size.xy = load i32, i32 addrspace(2)* %gep, align 4, !invariant.load !0
|
|
|
19 %workgroup.size.x = and i32 %workgroup.size.xy, 65535
|
|
|
20
|
|
|
21 %workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
|
|
|
22 %workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2
|
|
|
23
|
|
|
24 %mul = mul i32 %workgroup.id.x, %workgroup.size.x
|
|
|
25 %add = add i32 %mul, %workitem.id.x
|
|
|
26
|
|
|
27 store i32 %add, i32 addrspace(1)* %out, align 4
|
|
|
28 ret void
|
|
|
29 }
|
|
|
30
|
|
|
31 attributes #0 = { nounwind readnone }
|
|
|
32 attributes #1 = { nounwind }
|
|
|
33
|
|
|
34 !0 = !{}
|
|
|
35 !1 = !{i32 0, i32 1024}
|
|
|
36 !2 = !{i32 0, i32 16777216}
|
