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annotate test/CodeGen/Hexagon/vect/vect-shift-imm.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents afa8332a0e37
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
afa8332a0e37 LLVM 3.8
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2 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
afa8332a0e37 LLVM 3.8
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3 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
afa8332a0e37 LLVM 3.8
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6 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
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7 ;
afa8332a0e37 LLVM 3.8
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8 ; Make sure that the instructions with immediate operands are generated.
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803732b1fca8 LLVM 5.0
kono
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9 ; CHECK-ASLW: vaslw({{.*}},#9)
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10 ; CHECK-ASRW: vasrw({{.*}},#8)
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11 ; CHECK-LSRW: vlsrw({{.*}},#7)
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12 ; CHECK-ASLH: vaslh({{.*}},#6)
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13 ; CHECK-ASRH: vasrh({{.*}},#5)
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14 ; CHECK-LSRH: vlsrh({{.*}},#4)
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16 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
afa8332a0e37 LLVM 3.8
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17 target triple = "hexagon"
afa8332a0e37 LLVM 3.8
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afa8332a0e37 LLVM 3.8
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19 define i64 @foo(i64 %x) nounwind readnone {
afa8332a0e37 LLVM 3.8
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20 entry:
afa8332a0e37 LLVM 3.8
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21 %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
afa8332a0e37 LLVM 3.8
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22 %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
afa8332a0e37 LLVM 3.8
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23 %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
afa8332a0e37 LLVM 3.8
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24 %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
afa8332a0e37 LLVM 3.8
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25 %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
afa8332a0e37 LLVM 3.8
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26 %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
afa8332a0e37 LLVM 3.8
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27 %add = add i64 %1, %0
afa8332a0e37 LLVM 3.8
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28 %add1 = add i64 %add, %2
afa8332a0e37 LLVM 3.8
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29 %add2 = add i64 %add1, %3
afa8332a0e37 LLVM 3.8
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30 %add3 = add i64 %add2, %4
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31 %add4 = add i64 %add3, %5
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32 ret i64 %add4
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33 }
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35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
afa8332a0e37 LLVM 3.8
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36 declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
afa8332a0e37 LLVM 3.8
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37 declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
afa8332a0e37 LLVM 3.8
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38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
afa8332a0e37 LLVM 3.8
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39 declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
afa8332a0e37 LLVM 3.8
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40 declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone
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