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annotate lib/CodeGen/VirtRegMap.cpp @ 116:a609e5c42ecc

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change from CGF to this
author mir3636
date Mon, 08 Aug 2016 19:47:00 +0900
parents 7d135dc70f03
children 1172e4bd9c6f
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1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file implements the VirtRegMap class.
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11 //
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12 // It also contains implementations of the Spiller interface, which, given a
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13 // virtual register map and a machine function, eliminates all virtual
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14 // references by replacing them with physical register references - adding spill
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15 // code as necessary.
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16 //
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17 //===----------------------------------------------------------------------===//
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18
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19 #include "llvm/CodeGen/VirtRegMap.h"
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20 #include "LiveDebugVariables.h"
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21 #include "llvm/ADT/STLExtras.h"
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22 #include "llvm/ADT/SparseSet.h"
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23 #include "llvm/ADT/Statistic.h"
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24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
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25 #include "llvm/CodeGen/LiveStackAnalysis.h"
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26 #include "llvm/CodeGen/MachineFrameInfo.h"
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27 #include "llvm/CodeGen/MachineFunction.h"
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28 #include "llvm/CodeGen/MachineInstrBuilder.h"
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29 #include "llvm/CodeGen/MachineRegisterInfo.h"
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30 #include "llvm/CodeGen/Passes.h"
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31 #include "llvm/IR/Function.h"
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32 #include "llvm/Support/CommandLine.h"
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33 #include "llvm/Support/Compiler.h"
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34 #include "llvm/Support/Debug.h"
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35 #include "llvm/Support/raw_ostream.h"
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36 #include "llvm/Target/TargetInstrInfo.h"
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37 #include "llvm/Target/TargetMachine.h"
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38 #include "llvm/Target/TargetRegisterInfo.h"
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39 #include "llvm/Target/TargetSubtargetInfo.h"
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40 #include <algorithm>
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41 using namespace llvm;
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42
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43 #define DEBUG_TYPE "regalloc"
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44
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45 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
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46 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
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47
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48 //===----------------------------------------------------------------------===//
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49 // VirtRegMap implementation
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50 //===----------------------------------------------------------------------===//
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51
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52 char VirtRegMap::ID = 0;
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53
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54 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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55
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56 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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57 MRI = &mf.getRegInfo();
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58 TII = mf.getSubtarget().getInstrInfo();
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59 TRI = mf.getSubtarget().getRegisterInfo();
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60 MF = &mf;
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61
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62 Virt2PhysMap.clear();
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63 Virt2StackSlotMap.clear();
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64 Virt2SplitMap.clear();
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65
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66 grow();
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67 return false;
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68 }
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69
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70 void VirtRegMap::grow() {
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71 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
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72 Virt2PhysMap.resize(NumRegs);
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73 Virt2StackSlotMap.resize(NumRegs);
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74 Virt2SplitMap.resize(NumRegs);
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75 }
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76
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77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
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78 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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79 RC->getAlignment());
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80 ++NumSpillSlots;
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81 return SS;
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82 }
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83
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84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
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85 unsigned Hint = MRI->getSimpleHint(VirtReg);
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86 if (!Hint)
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87 return 0;
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88 if (TargetRegisterInfo::isVirtualRegister(Hint))
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89 Hint = getPhys(Hint);
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90 return getPhys(VirtReg) == Hint;
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91 }
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92
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93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
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94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
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95 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
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96 return true;
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97 if (TargetRegisterInfo::isVirtualRegister(Hint.second))
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98 return hasPhys(Hint.second);
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99 return false;
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100 }
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101
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102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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103 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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104 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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105 "attempt to assign stack slot to already spilled register");
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106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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108 }
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109
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110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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111 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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112 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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113 "attempt to assign stack slot to already spilled register");
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114 assert((SS >= 0 ||
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115 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
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116 "illegal fixed frame index");
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117 Virt2StackSlotMap[virtReg] = SS;
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118 }
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119
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120 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
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121 OS << "********** REGISTER MAP **********\n";
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122 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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123 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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124 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
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125 OS << '[' << PrintReg(Reg, TRI) << " -> "
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126 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
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127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
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128 }
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129 }
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130
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131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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132 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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133 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
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134 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
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135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
0
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136 }
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137 }
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138 OS << '\n';
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139 }
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140
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141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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142 void VirtRegMap::dump() const {
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143 print(dbgs());
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144 }
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145 #endif
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146
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147 //===----------------------------------------------------------------------===//
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148 // VirtRegRewriter
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149 //===----------------------------------------------------------------------===//
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150 //
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151 // The VirtRegRewriter is the last of the register allocator passes.
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152 // It rewrites virtual registers to physical registers as specified in the
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153 // VirtRegMap analysis. It also updates live-in information on basic blocks
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154 // according to LiveIntervals.
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155 //
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156 namespace {
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157 class VirtRegRewriter : public MachineFunctionPass {
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158 MachineFunction *MF;
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159 const TargetMachine *TM;
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160 const TargetRegisterInfo *TRI;
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161 const TargetInstrInfo *TII;
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162 MachineRegisterInfo *MRI;
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163 SlotIndexes *Indexes;
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164 LiveIntervals *LIS;
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165 VirtRegMap *VRM;
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166
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167 void rewrite();
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168 void addMBBLiveIns();
95
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169 bool readsUndefSubreg(const MachineOperand &MO) const;
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170 void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
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171
0
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172 public:
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173 static char ID;
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174 VirtRegRewriter() : MachineFunctionPass(ID) {}
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175
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176 void getAnalysisUsage(AnalysisUsage &AU) const override;
0
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177
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178 bool runOnMachineFunction(MachineFunction&) override;
0
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179 };
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180 } // end anonymous namespace
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181
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182 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
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183
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184 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
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185 "Virtual Register Rewriter", false, false)
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186 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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187 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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188 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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189 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
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190 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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191 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
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192 "Virtual Register Rewriter", false, false)
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193
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194 char VirtRegRewriter::ID = 0;
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195
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196 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
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197 AU.setPreservesCFG();
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198 AU.addRequired<LiveIntervals>();
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199 AU.addRequired<SlotIndexes>();
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200 AU.addPreserved<SlotIndexes>();
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201 AU.addRequired<LiveDebugVariables>();
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202 AU.addRequired<LiveStacks>();
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203 AU.addPreserved<LiveStacks>();
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204 AU.addRequired<VirtRegMap>();
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205 MachineFunctionPass::getAnalysisUsage(AU);
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206 }
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207
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208 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
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209 MF = &fn;
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210 TM = &MF->getTarget();
83
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diff changeset
211 TRI = MF->getSubtarget().getRegisterInfo();
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212 TII = MF->getSubtarget().getInstrInfo();
0
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213 MRI = &MF->getRegInfo();
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214 Indexes = &getAnalysis<SlotIndexes>();
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215 LIS = &getAnalysis<LiveIntervals>();
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216 VRM = &getAnalysis<VirtRegMap>();
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diff changeset
217 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
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diff changeset
218 << "********** Function: "
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diff changeset
219 << MF->getName() << '\n');
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220 DEBUG(VRM->dump());
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221
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222 // Add kill flags while we still have virtual registers.
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223 LIS->addKillFlags(VRM);
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diff changeset
224
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225 // Live-in lists on basic blocks are required for physregs.
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226 addMBBLiveIns();
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227
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228 // Rewrite virtual registers.
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229 rewrite();
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230
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231 // Write out new DBG_VALUE instructions.
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232 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
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diff changeset
233
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234 // All machine operands and other references to virtual registers have been
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235 // replaced. Remove the virtual registers and release all the transient data.
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diff changeset
236 VRM->clearAllVirt();
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diff changeset
237 MRI->clearVirtRegs();
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diff changeset
238 return true;
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239 }
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240
95
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241 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
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diff changeset
242 unsigned PhysReg) const {
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243 assert(!LI.empty());
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244 assert(LI.hasSubRanges());
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245
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246 typedef std::pair<const LiveInterval::SubRange *,
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diff changeset
247 LiveInterval::const_iterator> SubRangeIteratorPair;
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diff changeset
248 SmallVector<SubRangeIteratorPair, 4> SubRanges;
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249 SlotIndex First;
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250 SlotIndex Last;
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diff changeset
251 for (const LiveInterval::SubRange &SR : LI.subranges()) {
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diff changeset
252 SubRanges.push_back(std::make_pair(&SR, SR.begin()));
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diff changeset
253 if (!First.isValid() || SR.segments.front().start < First)
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254 First = SR.segments.front().start;
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diff changeset
255 if (!Last.isValid() || SR.segments.back().end > Last)
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diff changeset
256 Last = SR.segments.back().end;
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diff changeset
257 }
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258
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259 // Check all mbb start positions between First and Last while
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diff changeset
260 // simulatenously advancing an iterator for each subrange.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
261 for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
262 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
263 SlotIndex MBBBegin = MBBI->first;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
264 // Advance all subrange iterators so that their end position is just
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
265 // behind MBBBegin (or the iterator is at the end).
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
266 LaneBitmask LaneMask = 0;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
267 for (auto &RangeIterPair : SubRanges) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
268 const LiveInterval::SubRange *SR = RangeIterPair.first;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
269 LiveInterval::const_iterator &SRI = RangeIterPair.second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
270 while (SRI != SR->end() && SRI->end <= MBBBegin)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
271 ++SRI;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
272 if (SRI == SR->end())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
273 continue;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
274 if (SRI->start <= MBBBegin)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
275 LaneMask |= SR->LaneMask;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
276 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
277 if (LaneMask == 0)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
278 continue;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
279 MachineBasicBlock *MBB = MBBI->second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
280 MBB->addLiveIn(PhysReg, LaneMask);
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parents: 83
diff changeset
281 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
282 }
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parents: 83
diff changeset
283
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 // Compute MBB live-in lists from virtual register live ranges and their
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 // assignments.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 void VirtRegRewriter::addMBBLiveIns() {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 if (MRI->reg_nodbg_empty(VirtReg))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 LiveInterval &LI = LIS->getInterval(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 if (LI.empty() || LIS->intervalIsInOneMBB(LI))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 // This is a virtual register that is live across basic blocks. Its
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 // assigned PhysReg must be marked as live-in to those blocks.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 unsigned PhysReg = VRM->getPhys(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
298
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
299 if (LI.hasSubRanges()) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
300 addLiveInsForSubRanges(LI, PhysReg);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
301 } else {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
302 // Go over MBB begin positions and see if we have segments covering them.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
303 // The following works because segments and the MBBIndex list are both
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
304 // sorted by slot indexes.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
305 SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
306 for (const auto &Seg : LI) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
307 I = Indexes->advanceMBBIndex(I, Seg.start);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
308 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
309 MachineBasicBlock *MBB = I->second;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
310 MBB->addLiveIn(PhysReg);
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
311 }
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
312 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
315
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
316 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
317 // each MBB's LiveIns set before calling addLiveIn on them.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
318 for (MachineBasicBlock &MBB : *MF)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
319 MBB.sortUniqueLiveIns();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
320 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
321
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
322 /// Returns true if the given machine operand \p MO only reads undefined lanes.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
323 /// The function only works for use operands with a subregister set.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
324 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
325 // Shortcut if the operand is already marked undef.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
326 if (MO.isUndef())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
327 return true;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
328
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
329 unsigned Reg = MO.getReg();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
330 const LiveInterval &LI = LIS->getInterval(Reg);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
331 const MachineInstr &MI = *MO.getParent();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
332 SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
333 // This code is only meant to handle reading undefined subregisters which
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
334 // we couldn't properly detect before.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
335 assert(LI.liveAt(BaseIndex) &&
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
336 "Reads of completely dead register should be marked undef already");
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
337 unsigned SubRegIdx = MO.getSubReg();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
338 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
339 // See if any of the relevant subregister liveranges is defined at this point.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
340 for (const LiveInterval::SubRange &SR : LI.subranges()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
341 if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
342 return false;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
343 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
344 return true;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
346
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 void VirtRegRewriter::rewrite() {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
348 bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 SmallVector<unsigned, 8> SuperDeads;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 SmallVector<unsigned, 8> SuperDefs;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 SmallVector<unsigned, 8> SuperKills;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
352
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
353 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
354 MBBI != MBBE; ++MBBI) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
355 DEBUG(MBBI->print(dbgs(), Indexes));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
356 for (MachineBasicBlock::instr_iterator
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
357 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
358 MachineInstr *MI = &*MII;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
359 ++MII;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
360
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
361 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 MachineOperand &MO = *MOI;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
364
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 // Make sure MRI knows about registers clobbered by regmasks.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 if (MO.isRegMask())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
368
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
369 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
370 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 unsigned VirtReg = MO.getReg();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
372 unsigned PhysReg = VRM->getPhys(VirtReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
373 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 "Instruction uses unmapped VirtReg");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
376
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 // Preserve semantics of sub-register operands.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
378 unsigned SubReg = MO.getSubReg();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
379 if (SubReg != 0) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
380 if (NoSubRegLiveness) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
381 // A virtual register kill refers to the whole register, so we may
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
382 // have to add <imp-use,kill> operands for the super-register. A
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
383 // partial redef always kills and redefines the super-register.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
384 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
385 SuperKills.push_back(PhysReg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
386
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
387 if (MO.isDef()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
388 // Also add implicit defs for the super-register.
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
389 if (MO.isDead())
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
390 SuperDeads.push_back(PhysReg);
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
391 else
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
392 SuperDefs.push_back(PhysReg);
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
393 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
394 } else {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
395 if (MO.isUse()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
396 if (readsUndefSubreg(MO))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
397 // We need to add an <undef> flag if the subregister is
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
398 // completely undefined (and we are not adding super-register
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
399 // defs).
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
400 MO.setIsUndef(true);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
401 } else if (!MO.isDead()) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
402 assert(MO.isDef());
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
403 }
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
406 // The <def,undef> flag only makes sense for sub-register defs, and
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
407 // we are substituting a full physreg. An <imp-use,kill> operand
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
408 // from the SuperKills list will represent the partial read of the
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
409 // super-register.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
410 if (MO.isDef())
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
411 MO.setIsUndef(false);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
412
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 // PhysReg operands cannot have subregister indexes.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
414 PhysReg = TRI->getSubReg(PhysReg, SubReg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
415 assert(PhysReg && "Invalid SubReg for physical register");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
416 MO.setSubReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
417 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
418 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
419 // we need the inlining here.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 MO.setReg(PhysReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
422
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 // Add any missing super-register kills after rewriting the whole
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 // instruction.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 while (!SuperKills.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
427
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 while (!SuperDeads.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
430
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
431 while (!SuperDefs.empty())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
432 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
433
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
434 DEBUG(dbgs() << "> " << *MI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
435
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
436 // Finally, remove any identity copies.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 if (MI->isIdentityCopy()) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
438 ++NumIdCopies;
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
439 DEBUG(dbgs() << "Deleting identity copy.\n");
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
440 if (Indexes)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
441 Indexes->removeMachineInstrFromMaps(MI);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
442 // It's safe to erase MI because MII has already been incremented.
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
443 MI->eraseFromParent();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 }
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
448