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annotate test/CodeGen/AArch64/addsub.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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77
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1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
0
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2
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3 ; Note that this should be refactored (for efficiency if nothing else)
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4 ; when the PCS is implemented so we don't have to worry about the
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5 ; loads and stores.
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6
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7 @var_i32 = global i32 42
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8 @var_i64 = global i64 0
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9
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10 ; Add pure 12-bit immediates:
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parents:
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11 define void @add_small() {
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12 ; CHECK-LABEL: add_small:
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13
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parents:
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14 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
95
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15 %val32 = load i32, i32* @var_i32
0
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16 %newval32 = add i32 %val32, 4095
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parents:
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17 store i32 %newval32, i32* @var_i32
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18
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19 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52
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parents: 77
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20 %val64 = load i64, i64* @var_i64
0
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21 %newval64 = add i64 %val64, 52
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22 store i64 %newval64, i64* @var_i64
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23
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24 ret void
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parents:
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25 }
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26
95
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27 ; Make sure we grab the imm variant when the register operand
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28 ; can be implicitly zero-extend.
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29 ; We used to generate something horrible like this:
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30 ; wA = ldrb
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31 ; xB = ldimm 12
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32 ; xC = add xB, wA, uxtb
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33 ; whereas this can be achieved with:
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34 ; wA = ldrb
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35 ; xC = add xA, #12 ; <- xA implicitly zero extend wA.
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36 define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {
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37 ; CHECK-LABEL: add_small_imm:
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38 entry:
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39
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40 ; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0]
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41 %t = load i8, i8* %p
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42 %promoted = zext i8 %t to i64
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43 %zextt = zext i8 %t to i32
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44 %add = add nuw i32 %zextt, %b
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45
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46 ; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12
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47 %add2 = add nuw i64 %promoted, 12
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48 store i32 %add, i32* %addr
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49
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50 ; CHECK: str [[ADD2]], [x1]
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parents: 77
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51 store i64 %add2, i64* %q
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52 ret void
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53 }
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54
0
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55 ; Add 12-bit immediates, shifted left by 12 bits
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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56 define void @add_med() {
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57 ; CHECK-LABEL: add_med:
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58
77
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59 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
95
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60 %val32 = load i32, i32* @var_i32
0
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61 %newval32 = add i32 %val32, 14610432 ; =0xdef000
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62 store i32 %newval32, i32* @var_i32
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63
77
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64 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
95
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65 %val64 = load i64, i64* @var_i64
0
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66 %newval64 = add i64 %val64, 16773120 ; =0xfff000
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67 store i64 %newval64, i64* @var_i64
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68
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69 ret void
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70 }
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71
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72 ; Subtract 12-bit immediates
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73 define void @sub_small() {
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74 ; CHECK-LABEL: sub_small:
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75
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76 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
95
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77 %val32 = load i32, i32* @var_i32
0
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78 %newval32 = sub i32 %val32, 4095
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79 store i32 %newval32, i32* @var_i32
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80
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81 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52
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82 %val64 = load i64, i64* @var_i64
0
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83 %newval64 = sub i64 %val64, 52
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84 store i64 %newval64, i64* @var_i64
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85
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86 ret void
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87 }
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88
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89 ; Subtract 12-bit immediates, shifted left by 12 bits
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90 define void @sub_med() {
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91 ; CHECK-LABEL: sub_med:
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92
77
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93 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
95
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94 %val32 = load i32, i32* @var_i32
0
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95 %newval32 = sub i32 %val32, 14610432 ; =0xdef000
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96 store i32 %newval32, i32* @var_i32
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97
77
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98 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
95
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99 %val64 = load i64, i64* @var_i64
0
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100 %newval64 = sub i64 %val64, 16773120 ; =0xfff000
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101 store i64 %newval64, i64* @var_i64
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102
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103 ret void
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104 }
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105
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106 define void @testing() {
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107 ; CHECK-LABEL: testing:
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108 %val = load i32, i32* @var_i32
0
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parents:
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109
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110 ; CHECK: cmp {{w[0-9]+}}, #4095
77
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parents: 0
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111 ; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]]
0
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parents:
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112 %cmp_pos_small = icmp ne i32 %val, 4095
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parents:
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113 br i1 %cmp_pos_small, label %ret, label %test2
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parents:
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114
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115 test2:
77
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116 ; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
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117 ; CHECK: b.lo [[RET]]
0
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118 %newval2 = add i32 %val, 1
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parents:
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119 store i32 %newval2, i32* @var_i32
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parents:
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120 %cmp_pos_big = icmp ult i32 %val, 14610432
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parents:
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121 br i1 %cmp_pos_big, label %ret, label %test3
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parents:
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122
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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123 test3:
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parents:
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124 ; CHECK: cmp {{w[0-9]+}}, #123
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
125 ; CHECK: b.lt [[RET]]
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
126 %newval3 = add i32 %val, 2
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
127 store i32 %newval3, i32* @var_i32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
128 %cmp_pos_slt = icmp slt i32 %val, 123
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
129 br i1 %cmp_pos_slt, label %ret, label %test4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 test4:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 ; CHECK: cmp {{w[0-9]+}}, #321
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
133 ; CHECK: b.gt [[RET]]
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 %newval4 = add i32 %val, 3
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 store i32 %newval4, i32* @var_i32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 %cmp_pos_sgt = icmp sgt i32 %val, 321
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 br i1 %cmp_pos_sgt, label %ret, label %test5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 test5:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 ; CHECK: cmn {{w[0-9]+}}, #444
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
141 ; CHECK: b.gt [[RET]]
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 %newval5 = add i32 %val, 4
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 store i32 %newval5, i32* @var_i32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 %cmp_neg_uge = icmp sgt i32 %val, -444
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 br i1 %cmp_neg_uge, label %ret, label %test6
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 test6:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 %newval6 = add i32 %val, 5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 store i32 %newval6, i32* @var_i32
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 ret:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 ret void
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 ; TODO: adds/subs