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annotate test/CodeGen/AArch64/sibling-call.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 54457678186b
children 1172e4bd9c6f
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54457678186b LLVM 3.6
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1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -aarch64-load-store-opt=0 | FileCheck %s
0
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2
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3 declare void @callee_stack0()
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4 declare void @callee_stack8([8 x i32], i64)
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5 declare void @callee_stack16([8 x i32], i64, i64)
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6
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7 define void @caller_to0_from0() nounwind {
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8 ; CHECK-LABEL: caller_to0_from0:
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9 ; CHECK-NEXT: // BB
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10 tail call void @callee_stack0()
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11 ret void
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12 ; CHECK-NEXT: b callee_stack0
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13 }
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14
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15 define void @caller_to0_from8([8 x i32], i64) nounwind{
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16 ; CHECK-LABEL: caller_to0_from8:
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17 ; CHECK-NEXT: // BB
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18
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19 tail call void @callee_stack0()
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20 ret void
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21 ; CHECK-NEXT: b callee_stack0
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22 }
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23
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24 define void @caller_to8_from0() {
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25 ; CHECK-LABEL: caller_to8_from0:
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26
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27 ; Caller isn't going to clean up any extra stack we allocate, so it
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28 ; can't be a tail call.
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29 tail call void @callee_stack8([8 x i32] undef, i64 42)
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30 ret void
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31 ; CHECK: bl callee_stack8
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32 }
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33
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34 define void @caller_to8_from8([8 x i32], i64 %a) {
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35 ; CHECK-LABEL: caller_to8_from8:
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36 ; CHECK-NOT: sub sp, sp,
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37
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38 ; This should reuse our stack area for the 42
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39 tail call void @callee_stack8([8 x i32] undef, i64 42)
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40 ret void
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41 ; CHECK: str {{x[0-9]+}}, [sp]
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42 ; CHECK-NEXT: b callee_stack8
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43 }
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44
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45 define void @caller_to16_from8([8 x i32], i64 %a) {
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46 ; CHECK-LABEL: caller_to16_from8:
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47
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48 ; Shouldn't be a tail call: we can't use SP+8 because our caller might
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49 ; have something there. This may sound obvious but implementation does
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50 ; some funky aligning.
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51 tail call void @callee_stack16([8 x i32] undef, i64 undef, i64 undef)
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52 ; CHECK: bl callee_stack16
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53 ret void
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54 }
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55
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56 define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
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57 ; CHECK-LABEL: caller_to8_from24:
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58 ; CHECK-NOT: sub sp, sp
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59
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60 ; Reuse our area, putting "42" at incoming sp
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61 tail call void @callee_stack8([8 x i32] undef, i64 42)
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62 ret void
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63 ; CHECK: str {{x[0-9]+}}, [sp]
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64 ; CHECK-NEXT: b callee_stack8
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65 }
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66
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67 define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
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68 ; CHECK-LABEL: caller_to16_from16:
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69 ; CHECK-NOT: sub sp, sp,
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70
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71 ; Here we want to make sure that both loads happen before the stores:
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72 ; otherwise either %a or %b will be wrongly clobbered.
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73 tail call void @callee_stack16([8 x i32] undef, i64 %b, i64 %a)
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74 ret void
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75
77
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76 ; CHECK: ldr [[VAL0:x[0-9]+]],
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77 ; CHECK: ldr [[VAL1:x[0-9]+]],
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78 ; CHECK: str [[VAL0]],
77
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79 ; CHECK: str [[VAL1]],
0
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80
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81 ; CHECK-NOT: add sp, sp,
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82 ; CHECK: b callee_stack16
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83 }
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84
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85 @func = global void(i32)* null
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86
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87 define void @indirect_tail() {
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88 ; CHECK-LABEL: indirect_tail:
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89 ; CHECK-NOT: sub sp, sp
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90
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91 %fptr = load void(i32)*, void(i32)** @func
0
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92 tail call void %fptr(i32 42)
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93 ret void
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94 ; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func]
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95 ; CHECK: movz w0, #{{42|0x2a}}
0
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96 ; CHECK: br [[FPTR]]
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97 }