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annotate test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
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children 7d135dc70f03
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95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s
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2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
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3 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s
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4
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5 declare i32 @llvm.r600.read.tidig.x() #0
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6 declare void @llvm.AMDGPU.barrier.local() #1
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7
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8 ; Function Attrs: nounwind
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9 ; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop:
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10 ; CHECK: BB0_1:
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11 ; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]],
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12 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]]
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13 ; SI-DAG: v_add_i32_e32 [[VADDR4:v[0-9]+]], vcc, 4, [[VADDR]]
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14 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]]
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15 ; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]]
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16 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]]
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17 ; SI-DAG: v_add_i32_e32 [[VADDR0x84:v[0-9]+]], vcc, 0x84, [[VADDR]]
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18 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]]
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19 ; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]]
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20 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]]
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21
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22 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:1
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23 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33
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24 ; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256
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25 ; CHECK: s_endpgm
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26 define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 {
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27 entry:
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28 %x.i = tail call i32 @llvm.r600.read.tidig.x() #0
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29 %mul = shl nsw i32 %x.i, 1
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30 br label %for.body
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31
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32 for.body: ; preds = %for.body, %entry
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33 %sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ]
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34 %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ]
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35 %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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36 tail call void @llvm.AMDGPU.barrier.local() #1
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37 %arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02
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38 %tmp = load float, float addrspace(3)* %arrayidx, align 4
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39 %add1 = add nsw i32 %offset.02, 1
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40 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1
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41 %tmp1 = load float, float addrspace(3)* %arrayidx2, align 4
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42 %add3 = add nsw i32 %offset.02, 32
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43 %arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3
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44 %tmp2 = load float, float addrspace(3)* %arrayidx4, align 4
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45 %add5 = add nsw i32 %offset.02, 33
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46 %arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5
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47 %tmp3 = load float, float addrspace(3)* %arrayidx6, align 4
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48 %add7 = add nsw i32 %offset.02, 64
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49 %arrayidx8 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add7
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50 %tmp4 = load float, float addrspace(3)* %arrayidx8, align 4
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51 %add9 = fadd float %tmp, %tmp1
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52 %add10 = fadd float %add9, %tmp2
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53 %add11 = fadd float %add10, %tmp3
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54 %add12 = fadd float %add11, %tmp4
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55 %add13 = fadd float %sum.03, %add12
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56 %inc = add nsw i32 %k.01, 1
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57 %add14 = add nsw i32 %offset.02, 97
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58 %exitcond = icmp eq i32 %inc, 8
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59 br i1 %exitcond, label %for.end, label %for.body
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60
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61 for.end: ; preds = %for.body
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62 %tmp5 = sext i32 %x.i to i64
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63 %arrayidx15 = getelementptr inbounds float, float addrspace(1)* %out, i64 %tmp5
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64 store float %add13, float addrspace(1)* %arrayidx15, align 4
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65 ret void
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66 }
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67
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68 attributes #0 = { nounwind readnone }
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69 attributes #1 = { noduplicate nounwind }
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70 attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }