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annotate test/CodeGen/AMDGPU/fetch-limits.r600.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
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children 1172e4bd9c6f
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afa8332a0e37 LLVM 3.8
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1 ; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
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2 ; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
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3 ; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
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4
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5 ; R600 supports 8 fetches in a clause
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6 ; CHECK: {{^}}fetch_limits_r600:
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7 ; CHECK: Fetch clause
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8 ; CHECK: Fetch clause
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9
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10 define void @fetch_limits_r600() #0 {
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11 entry:
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12 %0 = load <4 x float>, <4 x float> addrspace(8)* null
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13 %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
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14 %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
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15 %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
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16 %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
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17 %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
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18 %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
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19 %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
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20 %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
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21 %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1)
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22 %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1)
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23 %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1)
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24 %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1)
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25 %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1)
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26 %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1)
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27 %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1)
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28 %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1)
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29 %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
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30 %a = fadd <4 x float> %res0, %res1
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31 %b = fadd <4 x float> %res2, %res3
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32 %c = fadd <4 x float> %res4, %res5
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33 %d = fadd <4 x float> %res6, %res7
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34 %e = fadd <4 x float> %res8, %a
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35
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36 %bc = fadd <4 x float> %b, %c
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37 %de = fadd <4 x float> %d, %e
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38
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39 %bcde = fadd <4 x float> %bc, %de
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40
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41 call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1)
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42 ret void
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43 }
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44
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45 attributes #0 = { "ShaderType"="0" } ; Pixel Shader
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46
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47 declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
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48 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)