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annotate test/CodeGen/AMDGPU/shared-op-cycle.ll @ 95:afa8332a0e37

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents test/CodeGen/R600/shared-op-cycle.ll@60c9769439b8
children 1172e4bd9c6f
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95c75e76d11b LLVM 3.4
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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3 ; CHECK: {{^}}main:
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4 ; CHECK: MULADD_IEEE *
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5 ; CHECK-NOT: MULADD_IEEE *
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7 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 {
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8 %w0 = extractelement <4 x float> %reg0, i32 3
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9 %w1 = extractelement <4 x float> %reg1, i32 3
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10 %w2 = extractelement <4 x float> %reg2, i32 3
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11 %sq0 = fmul float %w0, %w0
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12 %r0 = fadd float %sq0, 2.0
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13 %sq1 = fmul float %w1, %w1
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14 %r1 = fadd float %sq1, 2.0
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15 %sq2 = fmul float %w2, %w2
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16 %r2 = fadd float %sq2, 2.0
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17 %v0 = insertelement <4 x float> undef, float %r0, i32 0
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18 %v1 = insertelement <4 x float> %v0, float %r1, i32 1
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19 %v2 = insertelement <4 x float> %v1, float %r2, i32 2
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20 %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2)
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21 %vecres = insertelement <4 x float> undef, float %res, i32 0
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22 call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
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23 ret void
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24 }
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26 ; Function Attrs: readnone
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27 declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
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29 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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31 attributes #0 = { "ShaderType"="1" }
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32 attributes #1 = { readnone }