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annotate test/CodeGen/AArch64/arm64-sminv.ll @ 117:facf19d07cd9

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check EHStack on EmitCall (CbC goto)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 24 Aug 2016 20:10:41 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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1 ; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s
77
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parents:
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2
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parents:
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3 define signext i8 @test_vminv_s8(<8 x i8> %a1) {
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parents:
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4 ; CHECK: test_vminv_s8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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5 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
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parents:
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6 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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parents:
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7 ; CHECK-NEXT: ret
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parents:
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8 entry:
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9 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)
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parents:
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10 %0 = trunc i32 %vminv.i to i8
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11 ret i8 %0
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parents:
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12 }
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parents:
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13
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parents:
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14 define signext i16 @test_vminv_s16(<4 x i16> %a1) {
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parents:
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15 ; CHECK: test_vminv_s16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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16 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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17 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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parents:
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18 ; CHECK-NEXT: ret
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parents:
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19 entry:
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20 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)
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21 %0 = trunc i32 %vminv.i to i16
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22 ret i16 %0
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parents:
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23 }
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parents:
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24
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parents:
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25 define i32 @test_vminv_s32(<2 x i32> %a1) {
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parents:
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26 ; CHECK: test_vminv_s32
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parents:
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27 ; 2 x i32 is not supported by the ISA, thus, this is a special case
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parents:
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28 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
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parents:
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29 ; CHECK-NEXT: fmov w0, s[[REGNUM]]
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parents:
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30 ; CHECK-NEXT: ret
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parents:
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31 entry:
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parents:
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32 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)
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33 ret i32 %vminv.i
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parents:
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34 }
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parents:
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35
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parents:
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36 define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
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parents:
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37 ; CHECK: test_vminvq_s8
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parents:
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38 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
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parents:
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39 ; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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parents:
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40 ; CHECK-NEXT: ret
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parents:
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41 entry:
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parents:
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42 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)
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parents:
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43 %0 = trunc i32 %vminv.i to i8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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44 ret i8 %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 }
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parents:
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46
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 ; CHECK: test_vminvq_s16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 ; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 ; CHECK-NEXT: ret
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parents:
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52 entry:
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parents:
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53 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
54 %0 = trunc i32 %vminv.i to i16
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55 ret i16 %0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58 define i32 @test_vminvq_s32(<4 x i32> %a1) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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59 ; CHECK: test_vminvq_s32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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60 ; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 ; CHECK-NEXT: fmov w0, [[REGNUM]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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62 ; CHECK-NEXT: ret
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parents:
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63 entry:
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parents:
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64 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 ret i32 %vminv.i
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parents:
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66 }
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parents:
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67
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
68 define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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69 ; CHECK-LABEL: test_vminv_s8_used_by_laneop:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
70 ; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1
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parents: 77
diff changeset
71 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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parents: 77
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72 ; CHECK-NEXT: ret
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parents: 77
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73 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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74 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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75 %1 = trunc i32 %0 to i8
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parents: 77
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76 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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parents: 77
diff changeset
77 ret <8 x i8> %2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
78 }
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parents: 77
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79
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parents: 77
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80 define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
afa8332a0e37 LLVM 3.8
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parents: 77
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81 ; CHECK-LABEL: test_vminv_s16_used_by_laneop:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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82 ; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1
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parents: 77
diff changeset
83 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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parents: 77
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84 ; CHECK-NEXT: ret
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parents: 77
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85 entry:
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parents: 77
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86 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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87 %1 = trunc i32 %0 to i16
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parents: 77
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88 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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parents: 77
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89 ret <4 x i16> %2
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parents: 77
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90 }
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parents: 77
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91
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parents: 77
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92 define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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93 ; CHECK-LABEL: test_vminv_s32_used_by_laneop:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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94 ; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
95 ; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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parents: 77
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96 ; CHECK-NEXT: ret
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parents: 77
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97 entry:
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parents: 77
diff changeset
98 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
99 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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parents: 77
diff changeset
100 ret <2 x i32> %1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
101 }
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parents: 77
diff changeset
102
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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103 define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
104 ; CHECK-LABEL: test_vminvq_s8_used_by_laneop:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
105 ; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
106 ; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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107 ; CHECK-NEXT: ret
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parents: 77
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108 entry:
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parents: 77
diff changeset
109 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
110 %1 = trunc i32 %0 to i8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
111 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
112 ret <16 x i8> %2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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113 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
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114
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parents: 77
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115 define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
116 ; CHECK-LABEL: test_vminvq_s16_used_by_laneop:
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
117 ; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
118 ; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
119 ; CHECK-NEXT: ret
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parents: 77
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120 entry:
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121 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)
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122 %1 = trunc i32 %0 to i16
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123 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3
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124 ret <8 x i16> %2
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125 }
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126
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127 define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
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128 ; CHECK-LABEL: test_vminvq_s32_used_by_laneop:
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129 ; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1
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130 ; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
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131 ; CHECK-NEXT: ret
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132 entry:
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133 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)
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134 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3
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135 ret <4 x i32> %1
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136 }
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137
77
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138 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
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139 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
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140 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
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141 declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)
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142 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
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143 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
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144