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comparison lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
parents 7d135dc70f03
children 803732b1fca8
comparison
equal deleted inserted replaced
101:34baf5011add 120:1172e4bd9c6f
25 /// WebAssembly-specific information for each MachineFunction. 25 /// WebAssembly-specific information for each MachineFunction.
26 class WebAssemblyFunctionInfo final : public MachineFunctionInfo { 26 class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
27 MachineFunction &MF; 27 MachineFunction &MF;
28 28
29 std::vector<MVT> Params; 29 std::vector<MVT> Params;
30 std::vector<MVT> Results;
31 std::vector<MVT> Locals;
30 32
31 /// A mapping from CodeGen vreg index to WebAssembly register number. 33 /// A mapping from CodeGen vreg index to WebAssembly register number.
32 std::vector<unsigned> WARegs; 34 std::vector<unsigned> WARegs;
33 35
34 /// A mapping from CodeGen vreg index to a boolean value indicating whether 36 /// A mapping from CodeGen vreg index to a boolean value indicating whether
37 /// - single use (per path) 39 /// - single use (per path)
38 /// - single def (per path) 40 /// - single def (per path)
39 /// - defined and used in LIFO order with other stack registers 41 /// - defined and used in LIFO order with other stack registers
40 BitVector VRegStackified; 42 BitVector VRegStackified;
41 43
42 // One entry for each possible target reg. we expect it to be small. 44 // A virtual register holding the pointer to the vararg buffer for vararg
43 std::vector<unsigned> PhysRegs; 45 // functions. It is created and set in TLI::LowerFormalArguments and read by
46 // TLI::LowerVASTART
47 unsigned VarargVreg = -1U;
44 48
45 public: 49 // A virtual register holding the base pointer for functions that have
46 explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) { 50 // overaligned values on the user stack.
47 PhysRegs.resize(WebAssembly::NUM_TARGET_REGS, -1U); 51 unsigned BasePtrVreg = -1U;
48 } 52
53 public:
54 explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
49 ~WebAssemblyFunctionInfo() override; 55 ~WebAssemblyFunctionInfo() override;
50 56
51 void addParam(MVT VT) { Params.push_back(VT); } 57 void addParam(MVT VT) { Params.push_back(VT); }
52 const std::vector<MVT> &getParams() const { return Params; } 58 const std::vector<MVT> &getParams() const { return Params; }
53 59
60 void addResult(MVT VT) { Results.push_back(VT); }
61 const std::vector<MVT> &getResults() const { return Results; }
62
63 void addLocal(MVT VT) { Locals.push_back(VT); }
64 const std::vector<MVT> &getLocals() const { return Locals; }
65
66 unsigned getVarargBufferVreg() const {
67 assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
68 return VarargVreg;
69 }
70 void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
71
72 unsigned getBasePointerVreg() const {
73 assert(BasePtrVreg != -1U && "Base ptr vreg hasn't been set");
74 return BasePtrVreg;
75 }
76 void setBasePointerVreg(unsigned Reg) { BasePtrVreg = Reg; }
77
54 static const unsigned UnusedReg = -1u; 78 static const unsigned UnusedReg = -1u;
55 79
56 void stackifyVReg(unsigned VReg) { 80 void stackifyVReg(unsigned VReg) {
81 assert(MF.getRegInfo().getUniqueVRegDef(VReg));
57 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size()) 82 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
58 VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1); 83 VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
59 VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg)); 84 VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
60 }
61 void unstackifyVReg(unsigned VReg) {
62 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
63 return;
64 VRegStackified.reset(TargetRegisterInfo::virtReg2Index(VReg));
65 } 85 }
66 bool isVRegStackified(unsigned VReg) const { 86 bool isVRegStackified(unsigned VReg) const {
67 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size()) 87 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
68 return false; 88 return false;
69 return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg)); 89 return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
74 assert(WAReg != UnusedReg); 94 assert(WAReg != UnusedReg);
75 assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size()); 95 assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
76 WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg; 96 WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg;
77 } 97 }
78 unsigned getWAReg(unsigned Reg) const { 98 unsigned getWAReg(unsigned Reg) const {
79 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 99 assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
80 assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size()); 100 return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
81 return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
82 }
83 return PhysRegs[Reg];
84 }
85 // If new virtual registers are created after initWARegs has been called,
86 // this function can be used to add WebAssembly register mappings for them.
87 void addWAReg(unsigned VReg, unsigned WAReg) {
88 assert(VReg = WARegs.size());
89 WARegs.push_back(WAReg);
90 } 101 }
91 102
92 void addPReg(unsigned PReg, unsigned WAReg) { 103 // For a given stackified WAReg, return the id number to print with push/pop.
93 assert(PReg < WebAssembly::NUM_TARGET_REGS); 104 static unsigned getWARegStackId(unsigned Reg) {
94 assert(WAReg < -1U); 105 assert(Reg & INT32_MIN);
95 PhysRegs[PReg] = WAReg; 106 return Reg & INT32_MAX;
96 } 107 }
97 const std::vector<unsigned> &getPhysRegs() const { return PhysRegs; }
98 }; 108 };
109
110 void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
111 Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
112
113 void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
114 SmallVectorImpl<MVT> &Params,
115 SmallVectorImpl<MVT> &Results);
99 116
100 } // end namespace llvm 117 } // end namespace llvm
101 118
102 #endif 119 #endif