Mercurial > hg > Members > tobaru > cbc > CbC_llvm
comparison lib/Target/R600/AMDGPUSubtarget.cpp @ 77:54457678186b
LLVM 3.6
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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date | Mon, 08 Sep 2014 22:06:00 +0900 |
parents | e4204d083e25 |
children | 60c9769439b8 |
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34:e874dbf0ad9d | 77:54457678186b |
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11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget. | 11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget. |
12 // | 12 // |
13 //===----------------------------------------------------------------------===// | 13 //===----------------------------------------------------------------------===// |
14 | 14 |
15 #include "AMDGPUSubtarget.h" | 15 #include "AMDGPUSubtarget.h" |
16 #include "R600ISelLowering.h" | |
17 #include "R600InstrInfo.h" | |
18 #include "R600MachineScheduler.h" | |
19 #include "SIInstrInfo.h" | |
20 #include "SIISelLowering.h" | |
21 #include "llvm/ADT/SmallString.h" | |
22 | |
23 #include "llvm/ADT/SmallString.h" | |
16 | 24 |
17 using namespace llvm; | 25 using namespace llvm; |
26 | |
27 #define DEBUG_TYPE "amdgpu-subtarget" | |
18 | 28 |
19 #define GET_SUBTARGETINFO_ENUM | 29 #define GET_SUBTARGETINFO_ENUM |
20 #define GET_SUBTARGETINFO_TARGET_DESC | 30 #define GET_SUBTARGETINFO_TARGET_DESC |
21 #define GET_SUBTARGETINFO_CTOR | 31 #define GET_SUBTARGETINFO_CTOR |
22 #include "AMDGPUGenSubtargetInfo.inc" | 32 #include "AMDGPUGenSubtargetInfo.inc" |
23 | 33 |
24 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : | 34 static std::string computeDataLayout(const AMDGPUSubtarget &ST) { |
25 AMDGPUGenSubtargetInfo(TT, CPU, FS), DumpCode(false) { | 35 std::string Ret = "e-p:32:32"; |
26 InstrItins = getInstrItineraryForCPU(CPU); | |
27 | 36 |
28 // Default card | 37 if (ST.is64bit()) { |
29 StringRef GPU = CPU; | 38 // 32-bit private, local, and region pointers. 64-bit global and constant. |
30 Is64bit = false; | 39 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"; |
31 DefaultSize[0] = 64; | 40 } |
32 DefaultSize[1] = 1; | 41 |
33 DefaultSize[2] = 1; | 42 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256" |
34 HasVertexCache = false; | 43 "-v512:512-v1024:1024-v2048:2048-n32:64"; |
35 TexVTXClauseSize = 0; | 44 |
36 Gen = AMDGPUSubtarget::R600; | 45 return Ret; |
37 FP64 = false; | |
38 CaymanISA = false; | |
39 EnableIRStructurizer = true; | |
40 EnableIfCvt = true; | |
41 ParseSubtargetFeatures(GPU, FS); | |
42 DevName = GPU; | |
43 } | 46 } |
44 | 47 |
45 bool | 48 AMDGPUSubtarget & |
46 AMDGPUSubtarget::is64bit() const { | 49 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef GPU, StringRef FS) { |
47 return Is64bit; | 50 // Determine default and user-specified characteristics |
51 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be | |
52 // enabled, but some instructions do not respect them and they run at the | |
53 // double precision rate, so don't enable by default. | |
54 // | |
55 // We want to be able to turn these off, but making this a subtarget feature | |
56 // for SI has the unhelpful behavior that it unsets everything else if you | |
57 // disable it. | |
58 | |
59 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,"); | |
60 FullFS += FS; | |
61 | |
62 ParseSubtargetFeatures(GPU, FullFS); | |
63 | |
64 // FIXME: I don't think think Evergreen has any useful support for | |
65 // denormals, but should be checked. Should we issue a warning somewhere | |
66 // if someone tries to enable these? | |
67 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { | |
68 FP32Denormals = false; | |
69 FP64Denormals = false; | |
70 } | |
71 return *this; | |
48 } | 72 } |
49 bool | 73 |
50 AMDGPUSubtarget::hasVertexCache() const { | 74 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS, |
51 return HasVertexCache; | 75 TargetMachine &TM) |
52 } | 76 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), |
53 short | 77 DumpCode(false), R600ALUInst(false), HasVertexCache(false), |
54 AMDGPUSubtarget::getTexVTXClauseSize() const { | 78 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), |
55 return TexVTXClauseSize; | 79 FP64Denormals(false), FP32Denormals(false), CaymanISA(false), |
56 } | 80 EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true), |
57 enum AMDGPUSubtarget::Generation | 81 WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), |
58 AMDGPUSubtarget::getGeneration() const { | 82 DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))), |
59 return Gen; | 83 FrameLowering(TargetFrameLowering::StackGrowsUp, |
60 } | 84 64 * 16, // Maximum stack alignment (long16) |
61 bool | 85 0), |
62 AMDGPUSubtarget::hasHWFP64() const { | 86 InstrItins(getInstrItineraryForCPU(GPU)) { |
63 return FP64; | 87 |
64 } | 88 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { |
65 bool | 89 InstrInfo.reset(new R600InstrInfo(*this)); |
66 AMDGPUSubtarget::hasCaymanISA() const { | 90 TLInfo.reset(new R600TargetLowering(TM)); |
67 return CaymanISA; | |
68 } | |
69 bool | |
70 AMDGPUSubtarget::IsIRStructurizerEnabled() const { | |
71 return EnableIRStructurizer; | |
72 } | |
73 bool | |
74 AMDGPUSubtarget::isIfCvtEnabled() const { | |
75 return EnableIfCvt; | |
76 } | |
77 bool | |
78 AMDGPUSubtarget::isTargetELF() const { | |
79 return false; | |
80 } | |
81 size_t | |
82 AMDGPUSubtarget::getDefaultSize(uint32_t dim) const { | |
83 if (dim > 2) { | |
84 return 1; | |
85 } else { | 91 } else { |
86 return DefaultSize[dim]; | 92 InstrInfo.reset(new SIInstrInfo(*this)); |
93 TLInfo.reset(new SITargetLowering(TM)); | |
87 } | 94 } |
88 } | 95 } |
89 | 96 |
90 std::string | 97 unsigned AMDGPUSubtarget::getStackEntrySize() const { |
91 AMDGPUSubtarget::getDataLayout() const { | 98 assert(getGeneration() <= NORTHERN_ISLANDS); |
92 std::string DataLayout = std::string( | 99 switch(getWavefrontSize()) { |
93 "e" | 100 case 16: |
94 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" | 101 return 8; |
95 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" | 102 case 32: |
96 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" | 103 return hasCaymanISA() ? 4 : 8; |
97 "-n32:64" | 104 case 64: |
98 ); | 105 return 4; |
99 | 106 default: |
100 if (hasHWFP64()) { | 107 llvm_unreachable("Illegal wavefront size."); |
101 DataLayout.append("-f64:64:64"); | |
102 } | 108 } |
103 | |
104 if (is64bit()) { | |
105 DataLayout.append("-p:64:64:64"); | |
106 } else { | |
107 DataLayout.append("-p:32:32:32"); | |
108 } | |
109 | |
110 if (Gen >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { | |
111 DataLayout.append("-p3:32:32:32"); | |
112 } | |
113 | |
114 return DataLayout; | |
115 } | 109 } |
116 | |
117 std::string | |
118 AMDGPUSubtarget::getDeviceName() const { | |
119 return DevName; | |
120 } |