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comparison test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
3 3
4 ; and can be eliminated 4 ; and can be eliminated
5 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range: 5 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
6 ; CHECK-NOT: v0 6 ; CHECK-NOT: v0
7 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0 7 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
8 define void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 { 8 define amdgpu_kernel void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
9 entry: 9 entry:
10 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0 10 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
11 %and = and i32 %id, 1023 11 %and = and i32 %id, 1023
12 store i32 %and, i32 addrspace(1)* %out, align 4 12 store i32 %and, i32 addrspace(1)* %out, align 4
13 ret void 13 ret void
14 } 14 }
15 15
16 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range: 16 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range:
17 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0 17 ; CHECK-NOT: v_and_b32
18 ; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]] 18 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
19 define void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 { 19 define amdgpu_kernel void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 {
20 entry: 20 entry:
21 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0 21 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
22 %and = and i32 %id, 511 22 %and = and i32 %id, 511
23 store i32 %and, i32 addrspace(1)* %out, align 4 23 store i32 %and, i32 addrspace(1)* %out, align 4
24 ret void 24 ret void
25 } 25 }
26 26
27 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1: 27 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1:
28 ; CHECK-NOT: v0 28 ; CHECK-NOT: v0
29 ; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0 29 ; CHECK-NOT: v_and_b32
30 ; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]] 30 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
31 define void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 { 31 define amdgpu_kernel void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 {
32 entry: 32 entry:
33 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1 33 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1
34 %and = and i32 %id, 255 34 %and = and i32 %id, 255
35 store i32 %and, i32 addrspace(1)* %out, align 4 35 store i32 %and, i32 addrspace(1)* %out, align 4
36 ret void 36 ret void