annotate test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll @ 121:803732b1fca8

LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children
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1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
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2 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s
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3
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4 ; and can be eliminated
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5 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range:
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6 ; CHECK-NOT: v0
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7 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
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8 define amdgpu_kernel void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 {
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9 entry:
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10 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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11 %and = and i32 %id, 1023
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12 store i32 %and, i32 addrspace(1)* %out, align 4
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13 ret void
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14 }
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15
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16 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range:
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17 ; CHECK-NOT: v_and_b32
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18 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
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19 define amdgpu_kernel void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 {
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20 entry:
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21 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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22 %and = and i32 %id, 511
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23 store i32 %and, i32 addrspace(1)* %out, align 4
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24 ret void
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25 }
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26
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27 ; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1:
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28 ; CHECK-NOT: v0
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29 ; CHECK-NOT: v_and_b32
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30 ; CHECK: {{flat|buffer}}_store_dword {{.*}}v0
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31 define amdgpu_kernel void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 {
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32 entry:
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33 %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1
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34 %and = and i32 %id, 255
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35 store i32 %and, i32 addrspace(1)* %out, align 4
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36 ret void
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37 }
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38
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39
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40 declare i32 @llvm.amdgcn.workitem.id.x() #1
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41
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42 attributes #0 = { norecurse nounwind }
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43 attributes #1 = { nounwind readnone }
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44
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45 !0 = !{i32 0, i32 1024}
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46 !1 = !{i32 0, i32 1023}