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comparison test/CodeGen/Hexagon/bit-has.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
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120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc -march=hexagon < %s | FileCheck %s
2 ; REQUIRES: asserts
3
4 ; This used to crash. Check for some sane output.
5 ; CHECK: sath
6
7 target triple = "hexagon"
8
9 define void @fred() local_unnamed_addr #0 {
10 b0:
11 %v1 = load i32, i32* undef, align 4
12 %v2 = tail call i32 @llvm.hexagon.A2.sath(i32 undef)
13 %v3 = and i32 %v1, 603979776
14 %v4 = trunc i32 %v3 to i30
15 switch i30 %v4, label %b22 [
16 i30 -536870912, label %b5
17 i30 -469762048, label %b6
18 ]
19
20 b5: ; preds = %b0
21 unreachable
22
23 b6: ; preds = %b0
24 %v7 = load i32, i32* undef, align 4
25 %v8 = sub nsw i32 65536, %v7
26 %v9 = load i32, i32* undef, align 4
27 %v10 = mul nsw i32 %v9, %v9
28 %v11 = zext i32 %v10 to i64
29 %v12 = mul nsw i32 %v2, %v8
30 %v13 = sext i32 %v12 to i64
31 %v14 = mul nsw i64 %v13, %v11
32 %v15 = trunc i64 %v14 to i32
33 %v16 = and i32 %v15, 2147483647
34 store i32 %v16, i32* undef, align 4
35 %v17 = lshr i64 %v14, 31
36 %v18 = trunc i64 %v17 to i32
37 store i32 %v18, i32* undef, align 4
38 br label %b19
39
40 b19: ; preds = %b6
41 br i1 undef, label %b20, label %b21
42
43 b20: ; preds = %b19
44 unreachable
45
46 b21: ; preds = %b19
47 br label %b23
48
49 b22: ; preds = %b0
50 unreachable
51
52 b23: ; preds = %b21
53 %v24 = load i32, i32* undef, align 4
54 %v25 = shl i32 %v24, 1
55 %v26 = and i32 %v25, 65534
56 %v27 = or i32 %v26, 0
57 store i32 %v27, i32* undef, align 4
58 ret void
59 }
60
61 declare i32 @llvm.hexagon.A2.sath(i32) #1
62
63 attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" }
64 attributes #1 = { nounwind readnone }