view test/CodeGen/AMDGPU/fold-cndmask.mir @ 128:c347d3398279 default tip

fix
author mir3636
date Wed, 06 Dec 2017 14:37:17 +0900
parents 803732b1fca8
children
line wrap: on
line source

# RUN: llc -march=amdgcn -run-pass si-fold-operands -verify-machineinstrs -o - %s | FileCheck %s

# CHECK: %1:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
# CHECK: %2:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
# CHECK: %4:vgpr_32 = COPY %3
# CHECK: %5:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
# CHECK: %6:vgpr_32 = V_MOV_B32_e32 0, implicit %exec
# CHECK: %7:vgpr_32 = COPY %3

---
name:            fold_cndmask
tracksRegLiveness: true
registers:
  - { id: 0, class: sgpr_64 }
  - { id: 1, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }
  - { id: 4, class: vgpr_32 }
  - { id: 5, class: vgpr_32 }
  - { id: 6, class: vgpr_32 }
  - { id: 7, class: vgpr_32 }
body:             |
  bb.0.entry:
    %0 = IMPLICIT_DEF
    %1 = V_CNDMASK_B32_e64 0, 0, %0, implicit %exec
    %2 = V_CNDMASK_B32_e64 %1, %1, %0, implicit %exec
    %3 = IMPLICIT_DEF
    %4 = V_CNDMASK_B32_e64 %3, %3, %0, implicit %exec
    %5 = COPY %1
    %6 = V_CNDMASK_B32_e64 %5, 0, %0, implicit %exec
    %vcc = IMPLICIT_DEF
    %7 = V_CNDMASK_B32_e32 %3, %3, implicit %exec, implicit %vcc

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