Mercurial > hg > Members > tobaru > cbc > CbC_llvm
view test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @ 128:c347d3398279 default tip
fix
author | mir3636 |
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date | Wed, 06 Dec 2017 14:37:17 +0900 |
parents | 803732b1fca8 |
children |
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; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t ; RUN: FileCheck %s < %t ; REQUIRES: asserts ; Make sure that mayalias store-load dependencies have one cycle ; latency regardless of whether they are barriers or not. ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}}Volatile ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(2): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}} ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(2): Ord Latency=1 ; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4 %0 = load volatile i32, i32* %p2, align 4 ret i32 %0 } define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store i32 65540, i32* %p1, align 4 %0 = load i32, i32* %p2, align 4 ret i32 %0 }