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annotate lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @ 120:1172e4bd9c6f

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update 4.0.0
author mir3636
date Fri, 25 Nov 2016 19:14:25 +0900
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children 803732b1fca8
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1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file is part of the Sparc Disassembler.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "Sparc.h"
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15 #include "SparcRegisterInfo.h"
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16 #include "SparcSubtarget.h"
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17 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
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18 #include "llvm/MC/MCFixedLenDisassembler.h"
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19 #include "llvm/MC/MCInst.h"
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20 #include "llvm/MC/MCContext.h"
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21 #include "llvm/MC/MCAsmInfo.h"
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22 #include "llvm/Support/TargetRegistry.h"
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23
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24 using namespace llvm;
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25
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26 #define DEBUG_TYPE "sparc-disassembler"
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27
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28 typedef MCDisassembler::DecodeStatus DecodeStatus;
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29
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30 namespace {
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31
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32 /// A disassembler class for Sparc.
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33 class SparcDisassembler : public MCDisassembler {
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34 public:
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35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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36 : MCDisassembler(STI, Ctx) {}
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37 virtual ~SparcDisassembler() {}
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38
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39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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40 ArrayRef<uint8_t> Bytes, uint64_t Address,
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41 raw_ostream &VStream,
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42 raw_ostream &CStream) const override;
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43 };
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44 }
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45
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46 namespace llvm {
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47 Target &getTheSparcTarget();
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48 Target &getTheSparcV9Target();
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49 Target &getTheSparcelTarget();
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50 }
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51
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52 static MCDisassembler *createSparcDisassembler(const Target &T,
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53 const MCSubtargetInfo &STI,
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54 MCContext &Ctx) {
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55 return new SparcDisassembler(STI, Ctx);
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56 }
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57
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58
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59 extern "C" void LLVMInitializeSparcDisassembler() {
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60 // Register the disassembler.
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61 TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(),
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62 createSparcDisassembler);
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63 TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(),
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64 createSparcDisassembler);
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65 TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(),
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66 createSparcDisassembler);
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67 }
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68
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69 static const unsigned IntRegDecoderTable[] = {
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70 SP::G0, SP::G1, SP::G2, SP::G3,
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71 SP::G4, SP::G5, SP::G6, SP::G7,
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72 SP::O0, SP::O1, SP::O2, SP::O3,
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73 SP::O4, SP::O5, SP::O6, SP::O7,
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74 SP::L0, SP::L1, SP::L2, SP::L3,
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75 SP::L4, SP::L5, SP::L6, SP::L7,
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76 SP::I0, SP::I1, SP::I2, SP::I3,
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77 SP::I4, SP::I5, SP::I6, SP::I7 };
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78
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79 static const unsigned FPRegDecoderTable[] = {
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80 SP::F0, SP::F1, SP::F2, SP::F3,
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81 SP::F4, SP::F5, SP::F6, SP::F7,
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82 SP::F8, SP::F9, SP::F10, SP::F11,
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83 SP::F12, SP::F13, SP::F14, SP::F15,
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84 SP::F16, SP::F17, SP::F18, SP::F19,
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85 SP::F20, SP::F21, SP::F22, SP::F23,
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86 SP::F24, SP::F25, SP::F26, SP::F27,
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87 SP::F28, SP::F29, SP::F30, SP::F31 };
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88
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89 static const unsigned DFPRegDecoderTable[] = {
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90 SP::D0, SP::D16, SP::D1, SP::D17,
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91 SP::D2, SP::D18, SP::D3, SP::D19,
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92 SP::D4, SP::D20, SP::D5, SP::D21,
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93 SP::D6, SP::D22, SP::D7, SP::D23,
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94 SP::D8, SP::D24, SP::D9, SP::D25,
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95 SP::D10, SP::D26, SP::D11, SP::D27,
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96 SP::D12, SP::D28, SP::D13, SP::D29,
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97 SP::D14, SP::D30, SP::D15, SP::D31 };
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98
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99 static const unsigned QFPRegDecoderTable[] = {
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100 SP::Q0, SP::Q8, ~0U, ~0U,
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101 SP::Q1, SP::Q9, ~0U, ~0U,
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102 SP::Q2, SP::Q10, ~0U, ~0U,
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103 SP::Q3, SP::Q11, ~0U, ~0U,
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104 SP::Q4, SP::Q12, ~0U, ~0U,
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105 SP::Q5, SP::Q13, ~0U, ~0U,
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106 SP::Q6, SP::Q14, ~0U, ~0U,
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107 SP::Q7, SP::Q15, ~0U, ~0U } ;
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108
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109 static const unsigned FCCRegDecoderTable[] = {
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110 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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111
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112 static const unsigned ASRRegDecoderTable[] = {
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113 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
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114 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
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115 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
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116 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
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117 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
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118 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
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119 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
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120 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
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121
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122 static const unsigned PRRegDecoderTable[] = {
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123 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
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124 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
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125 SP::OTHERWIN, SP::WSTATE
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126 };
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127
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128 static const uint16_t IntPairDecoderTable[] = {
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129 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
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130 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
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131 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
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132 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
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133 };
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134
120
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135 static const unsigned CPRegDecoderTable[] = {
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136 SP::C0, SP::C1, SP::C2, SP::C3,
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137 SP::C4, SP::C5, SP::C6, SP::C7,
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138 SP::C8, SP::C9, SP::C10, SP::C11,
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139 SP::C12, SP::C13, SP::C14, SP::C15,
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140 SP::C16, SP::C17, SP::C18, SP::C19,
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141 SP::C20, SP::C21, SP::C22, SP::C23,
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142 SP::C24, SP::C25, SP::C26, SP::C27,
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143 SP::C28, SP::C29, SP::C30, SP::C31
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144 };
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145
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146
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147 static const uint16_t CPPairDecoderTable[] = {
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148 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
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149 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
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150 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
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151 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
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152 };
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153
77
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154 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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155 unsigned RegNo,
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parents:
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156 uint64_t Address,
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157 const void *Decoder) {
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158 if (RegNo > 31)
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159 return MCDisassembler::Fail;
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diff changeset
160 unsigned Reg = IntRegDecoderTable[RegNo];
95
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161 Inst.addOperand(MCOperand::createReg(Reg));
77
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162 return MCDisassembler::Success;
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163 }
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164
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165 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
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166 unsigned RegNo,
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parents:
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167 uint64_t Address,
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168 const void *Decoder) {
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diff changeset
169 if (RegNo > 31)
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170 return MCDisassembler::Fail;
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diff changeset
171 unsigned Reg = IntRegDecoderTable[RegNo];
95
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172 Inst.addOperand(MCOperand::createReg(Reg));
77
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173 return MCDisassembler::Success;
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parents:
diff changeset
174 }
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175
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176
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177 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
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diff changeset
178 unsigned RegNo,
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parents:
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179 uint64_t Address,
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diff changeset
180 const void *Decoder) {
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parents:
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181 if (RegNo > 31)
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diff changeset
182 return MCDisassembler::Fail;
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parents:
diff changeset
183 unsigned Reg = FPRegDecoderTable[RegNo];
95
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diff changeset
184 Inst.addOperand(MCOperand::createReg(Reg));
77
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185 return MCDisassembler::Success;
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diff changeset
186 }
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187
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188
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189 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
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diff changeset
190 unsigned RegNo,
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parents:
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191 uint64_t Address,
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parents:
diff changeset
192 const void *Decoder) {
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parents:
diff changeset
193 if (RegNo > 31)
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parents:
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194 return MCDisassembler::Fail;
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parents:
diff changeset
195 unsigned Reg = DFPRegDecoderTable[RegNo];
95
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diff changeset
196 Inst.addOperand(MCOperand::createReg(Reg));
77
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197 return MCDisassembler::Success;
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diff changeset
198 }
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diff changeset
199
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diff changeset
200
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diff changeset
201 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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parents:
diff changeset
202 unsigned RegNo,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 uint64_t Address,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 const void *Decoder) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 if (RegNo > 31)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 return MCDisassembler::Fail;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
207
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 unsigned Reg = QFPRegDecoderTable[RegNo];
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 if (Reg == ~0U)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 return MCDisassembler::Fail;
95
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
211 Inst.addOperand(MCOperand::createReg(Reg));
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 }
54457678186b LLVM 3.6
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parents:
diff changeset
214
120
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diff changeset
215 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
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diff changeset
216 unsigned RegNo,
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diff changeset
217 uint64_t Address,
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diff changeset
218 const void *Decoder) {
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diff changeset
219 if (RegNo > 31)
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diff changeset
220 return MCDisassembler::Fail;
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diff changeset
221 unsigned Reg = CPRegDecoderTable[RegNo];
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diff changeset
222 Inst.addOperand(MCOperand::createReg(Reg));
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diff changeset
223 return MCDisassembler::Success;
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diff changeset
224 }
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diff changeset
225
77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
226 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
227 uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
229 if (RegNo > 3)
54457678186b LLVM 3.6
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parents:
diff changeset
230 return MCDisassembler::Fail;
95
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
231 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
232 return MCDisassembler::Success;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
233 }
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
234
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
235 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
236 uint64_t Address,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
237 const void *Decoder) {
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
238 if (RegNo > 31)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
239 return MCDisassembler::Fail;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
240 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
95
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
244 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
245 uint64_t Address,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
246 const void *Decoder) {
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
247 if (RegNo >= array_lengthof(PRRegDecoderTable))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
248 return MCDisassembler::Fail;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
249 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
250 return MCDisassembler::Success;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
251 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
252
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
253 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
254 uint64_t Address, const void *Decoder) {
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
255 DecodeStatus S = MCDisassembler::Success;
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
256
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
257 if (RegNo > 31)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
258 return MCDisassembler::Fail;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
259
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
260 if ((RegNo & 1))
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
261 S = MCDisassembler::SoftFail;
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
262
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
263 unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
264 Inst.addOperand(MCOperand::createReg(RegisterPair));
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
265 return S;
afa8332a0e37 LLVM 3.8
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parents: 83
diff changeset
266 }
77
54457678186b LLVM 3.6
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parents:
diff changeset
267
120
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mir3636
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diff changeset
268 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
269 uint64_t Address, const void *Decoder) {
1172e4bd9c6f update 4.0.0
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parents: 95
diff changeset
270 if (RegNo > 31)
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diff changeset
271 return MCDisassembler::Fail;
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diff changeset
272
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diff changeset
273 unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
1172e4bd9c6f update 4.0.0
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diff changeset
274 Inst.addOperand(MCOperand::createReg(RegisterPair));
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diff changeset
275 return MCDisassembler::Success;
1172e4bd9c6f update 4.0.0
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parents: 95
diff changeset
276 }
1172e4bd9c6f update 4.0.0
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diff changeset
277
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 const void *Decoder);
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
280 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
281 const void *Decoder);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 const void *Decoder);
120
1172e4bd9c6f update 4.0.0
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parents: 95
diff changeset
288 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
1172e4bd9c6f update 4.0.0
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parents: 95
diff changeset
289 const void *Decoder);
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mir3636
parents: 95
diff changeset
290 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
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parents: 95
diff changeset
291 const void *Decoder);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 uint64_t Address, const void *Decoder);
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
294 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
295 uint64_t Address, const void *Decoder);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 uint64_t Address, const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 uint64_t Address, const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 uint64_t Address, const void *Decoder);
120
1172e4bd9c6f update 4.0.0
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parents: 95
diff changeset
302 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
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diff changeset
303 uint64_t Address, const void *Decoder);
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parents: 95
diff changeset
304 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
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parents: 95
diff changeset
305 uint64_t Address, const void *Decoder);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 uint64_t Address, const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 uint64_t Address, const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
310 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 const void *Decoder);
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
316 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
317 const void *Decoder);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
318
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 #include "SparcGenDisassemblerTables.inc"
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
320
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
321 /// Read four bytes from the ArrayRef and return 32 bit word.
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
322 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
323 uint64_t &Size, uint32_t &Insn,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
324 bool IsLittleEndian) {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 // We want to read exactly 4 Bytes of data.
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
326 if (Bytes.size() < 4) {
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
327 Size = 0;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 return MCDisassembler::Fail;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
330
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
331 Insn = IsLittleEndian
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
332 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
333 (Bytes[3] << 24)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
334 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
335 (Bytes[0] << 24);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
336
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
339
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
340 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
341 ArrayRef<uint8_t> Bytes,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
342 uint64_t Address,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
343 raw_ostream &VStream,
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
344 raw_ostream &CStream) const {
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 uint32_t Insn;
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
346 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
347 DecodeStatus Result =
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
348 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 if (Result == MCDisassembler::Fail)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 return MCDisassembler::Fail;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
351
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
352 // Calling the auto-generated decoder function.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
353
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
354 if (STI.getFeatureBits()[Sparc::FeatureV9])
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
355 {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
356 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
357 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
358 else
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
359 {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
360 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
361 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
362 if (Result != MCDisassembler::Fail)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
363 return Result;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
364
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
365 Result =
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
366 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
367
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 if (Result != MCDisassembler::Fail) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
369 Size = 4;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
370 return Result;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
372
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
373 return MCDisassembler::Fail;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
375
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
376
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 const void *Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
379
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 const void *Decoder,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 bool isLoad, DecodeFunc DecodeRD) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 unsigned rd = fieldFromInstruction(insn, 25, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
385 bool isImm = fieldFromInstruction(insn, 13, 1);
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
386 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
387 unsigned asi = fieldFromInstruction(insn, 5, 8);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
388 unsigned rs2 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 unsigned simm13 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 if (isImm)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
391 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
392 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 rs2 = fieldFromInstruction(insn, 0, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
394
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 DecodeStatus status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 if (isLoad) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 status = DecodeRD(MI, rd, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
400 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
401
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
402 // Decode rs1.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
406
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 // Decode imm|rs2.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 if (isImm)
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
409 MI.addOperand(MCOperand::createImm(simm13));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 else {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
414 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
415
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
416 if (hasAsi)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
417 MI.addOperand(MCOperand::createImm(asi));
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
418
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
419 if (!isLoad) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
420 status = DecodeRD(MI, rd, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
426
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 return DecodeMem(Inst, insn, Address, Decoder, true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
430 DecodeIntRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
431 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
432
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
433 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
434 const void *Decoder) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
435 return DecodeMem(Inst, insn, Address, Decoder, true,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
436 DecodeIntPairRegisterClass);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
437 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
438
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 return DecodeMem(Inst, insn, Address, Decoder, true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 DecodeFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
444
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
445 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
446 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
447 return DecodeMem(Inst, insn, Address, Decoder, true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
448 DecodeDFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
450
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 return DecodeMem(Inst, insn, Address, Decoder, true,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 DecodeQFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
455 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
456
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
457 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
458 const void *Decoder) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
459 return DecodeMem(Inst, insn, Address, Decoder, true,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
460 DecodeCPRegsRegisterClass);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
461 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
462
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
463 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
464 const void *Decoder) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
465 return DecodeMem(Inst, insn, Address, Decoder, true,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
466 DecodeCPPairRegisterClass);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
467 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
468
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 uint64_t Address, const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 return DecodeMem(Inst, insn, Address, Decoder, false,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 DecodeIntRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
474
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
475 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
476 uint64_t Address, const void *Decoder) {
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
477 return DecodeMem(Inst, insn, Address, Decoder, false,
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
478 DecodeIntPairRegisterClass);
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
479 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
480
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
481 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 return DecodeMem(Inst, insn, Address, Decoder, false,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
484 DecodeFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
485 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
486
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
487 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
488 uint64_t Address, const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
489 return DecodeMem(Inst, insn, Address, Decoder, false,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
490 DecodeDFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
492
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
493 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 uint64_t Address, const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 return DecodeMem(Inst, insn, Address, Decoder, false,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 DecodeQFPRegsRegisterClass);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
498
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
499 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
500 uint64_t Address, const void *Decoder) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
501 return DecodeMem(Inst, insn, Address, Decoder, false,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
502 DecodeCPRegsRegisterClass);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
503 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
504
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
505 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
506 uint64_t Address, const void *Decoder) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
507 return DecodeMem(Inst, insn, Address, Decoder, false,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
508 DecodeCPPairRegisterClass);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
509 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
510
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
511 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
512 uint64_t Address, uint64_t Offset,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
513 uint64_t Width, MCInst &MI,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
514 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
515 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
516 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
517 Offset, Width);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
518 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
519
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 uint64_t Address, const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
522 unsigned tgt = fieldFromInstruction(insn, 0, 30);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
523 tgt <<= 2;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
525 0, 30, MI, Decoder))
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
526 MI.addOperand(MCOperand::createImm(tgt));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
527 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
528 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
529
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
530 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
531 uint64_t Address, const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
532 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
533 MI.addOperand(MCOperand::createImm(tgt));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
535 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
536
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
537 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
539
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
540 unsigned rd = fieldFromInstruction(insn, 25, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
541 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
542 unsigned isImm = fieldFromInstruction(insn, 13, 1);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
543 unsigned rs2 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
544 unsigned simm13 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
545 if (isImm)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
546 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
547 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
548 rs2 = fieldFromInstruction(insn, 0, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
549
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
550 // Decode RD.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
551 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
552 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
553 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
554
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
555 // Decode RS1.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
556 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
557 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
558 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
559
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
560 // Decode RS1 | SIMM13.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
561 if (isImm)
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
562 MI.addOperand(MCOperand::createImm(simm13));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
563 else {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
564 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
565 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
566 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
567 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
568 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
569 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
570
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
571 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
572 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
573
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
574 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
575 unsigned isImm = fieldFromInstruction(insn, 13, 1);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
576 unsigned rs2 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
577 unsigned simm13 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
578 if (isImm)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
579 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
580 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
581 rs2 = fieldFromInstruction(insn, 0, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
582
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
583 // Decode RS1.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
584 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
585 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
586 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
587
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
588 // Decode RS2 | SIMM13.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
589 if (isImm)
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
590 MI.addOperand(MCOperand::createImm(simm13));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
591 else {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
592 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
593 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
594 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
595 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
596 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
597 }
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
598
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
599 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
600 const void *Decoder) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
601
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
602 unsigned rd = fieldFromInstruction(insn, 25, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
603 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
604 unsigned isImm = fieldFromInstruction(insn, 13, 1);
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
605 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
606 unsigned asi = fieldFromInstruction(insn, 5, 8);
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
607 unsigned rs2 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
608 unsigned simm13 = 0;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
609 if (isImm)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
610 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
611 else
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
612 rs2 = fieldFromInstruction(insn, 0, 5);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
613
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
614 // Decode RD.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
615 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
616 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
617 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
618
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
619 // Decode RS1.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
620 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
621 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
622 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
623
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
624 // Decode RS1 | SIMM13.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
625 if (isImm)
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
626 MI.addOperand(MCOperand::createImm(simm13));
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
627 else {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
628 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
629 if (status != MCDisassembler::Success)
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
630 return status;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
631 }
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
632
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
633 if (hasAsi)
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
634 MI.addOperand(MCOperand::createImm(asi));
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
635
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
636 return MCDisassembler::Success;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
637 }
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
638
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
639 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
640 const void *Decoder) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
641
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
642 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
643 unsigned isImm = fieldFromInstruction(insn, 13, 1);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
644 unsigned cc =fieldFromInstruction(insn, 25, 4);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
645 unsigned rs2 = 0;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
646 unsigned imm7 = 0;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
647 if (isImm)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
648 imm7 = fieldFromInstruction(insn, 0, 7);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
649 else
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
650 rs2 = fieldFromInstruction(insn, 0, 5);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
651
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
652 // Decode RS1.
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
653 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
654 if (status != MCDisassembler::Success)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
655 return status;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
656
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
657 // Decode RS1 | IMM7.
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
658 if (isImm)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
659 MI.addOperand(MCOperand::createImm(imm7));
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
660 else {
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
661 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
662 if (status != MCDisassembler::Success)
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
663 return status;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
664 }
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
665
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
666 // Decode CC
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
667 MI.addOperand(MCOperand::createImm(cc));
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
668
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
669 return MCDisassembler::Success;
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
670 }