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120
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE2
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3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=X64-SSSE3
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4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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5
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77
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6 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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7
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 define i32 @t(<2 x i64>* %val) nounwind {
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120
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9 ; X32-SSE2-LABEL: t:
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10 ; X32-SSE2: # BB#0:
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11 ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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12 ; X32-SSE2-NEXT: movl 8(%eax), %eax
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13 ; X32-SSE2-NEXT: retl
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14 ;
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15 ; X64-SSSE3-LABEL: t:
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16 ; X64-SSSE3: # BB#0:
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17 ; X64-SSSE3-NEXT: movl 8(%rdi), %eax
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18 ; X64-SSSE3-NEXT: retq
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19 ;
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20 ; X64-AVX-LABEL: t:
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21 ; X64-AVX: # BB#0:
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22 ; X64-AVX-NEXT: movl 8(%rdi), %eax
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23 ; X64-AVX-NEXT: retq
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24 %tmp2 = load <2 x i64>, <2 x i64>* %val, align 16 ; <<2 x i64>> [#uses=1]
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25 %tmp3 = bitcast <2 x i64> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1]
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26 %tmp4 = extractelement <4 x i32> %tmp3, i32 2 ; <i32> [#uses=1]
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27 ret i32 %tmp4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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28 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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29
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 ; Case where extractelement of load ends up as undef.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 ; (Making sure this doesn't crash.)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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32 define i32 @t2(<8 x i32>* %xp) {
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120
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33 ; X32-SSE2-LABEL: t2:
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34 ; X32-SSE2: # BB#0:
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35 ; X32-SSE2-NEXT: retl
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36 ;
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37 ; X64-SSSE3-LABEL: t2:
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38 ; X64-SSSE3: # BB#0:
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39 ; X64-SSSE3-NEXT: retq
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40 ;
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41 ; X64-AVX-LABEL: t2:
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42 ; X64-AVX: # BB#0:
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43 ; X64-AVX-NEXT: retq
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95
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44 %x = load <8 x i32>, <8 x i32>* %xp
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120
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45 %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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46 %y = extractelement <8 x i32> %Shuff68, i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 ret i32 %y
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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48 }
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77
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49
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50 ; This case could easily end up inf-looping in the DAG combiner due to an
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51 ; low alignment load of the vector which prevents us from reliably forming a
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52 ; narrow load.
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83
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53
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54 ; The expected codegen is identical for the AVX case except
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55 ; load/store instructions will have a leading 'v', so we don't
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56 ; need to special-case the checks.
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57
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77
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58 define void @t3() {
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120
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59 ; X32-SSE2-LABEL: t3:
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60 ; X32-SSE2: # BB#0: # %bb
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61 ; X32-SSE2-NEXT: movupd (%eax), %xmm0
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62 ; X32-SSE2-NEXT: movhpd %xmm0, (%eax)
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63 ;
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64 ; X64-SSSE3-LABEL: t3:
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65 ; X64-SSSE3: # BB#0: # %bb
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66 ; X64-SSSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
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67 ; X64-SSSE3-NEXT: movlpd %xmm0, (%rax)
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68 ;
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69 ; X64-AVX-LABEL: t3:
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70 ; X64-AVX: # BB#0: # %bb
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71 ; X64-AVX-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
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72 ; X64-AVX-NEXT: vmovlpd %xmm0, (%rax)
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77
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73 bb:
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95
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74 %tmp13 = load <2 x double>, <2 x double>* undef, align 1
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77
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75 %.sroa.3.24.vec.extract = extractelement <2 x double> %tmp13, i32 1
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76 store double %.sroa.3.24.vec.extract, double* undef, align 8
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77 unreachable
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78 }
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83
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79
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80 ; Case where a load is unary shuffled, then bitcast (to a type with the same
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81 ; number of elements) before extractelement.
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82 ; This is testing for an assertion - the extraction was assuming that the undef
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83 ; second shuffle operand was a post-bitcast type instead of a pre-bitcast type.
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84 define i64 @t4(<2 x double>* %a) {
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120
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85 ; X32-SSE2-LABEL: t4:
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86 ; X32-SSE2: # BB#0:
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87 ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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88 ; X32-SSE2-NEXT: movapd (%eax), %xmm0
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89 ; X32-SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1,0]
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90 ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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91 ; X32-SSE2-NEXT: movd %xmm1, %eax
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92 ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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93 ; X32-SSE2-NEXT: movd %xmm0, %edx
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94 ; X32-SSE2-NEXT: retl
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95 ;
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96 ; X64-SSSE3-LABEL: t4:
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97 ; X64-SSSE3: # BB#0:
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98 ; X64-SSSE3-NEXT: movq (%rdi), %rax
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99 ; X64-SSSE3-NEXT: retq
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100 ;
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101 ; X64-AVX-LABEL: t4:
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102 ; X64-AVX: # BB#0:
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103 ; X64-AVX-NEXT: movq (%rdi), %rax
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104 ; X64-AVX-NEXT: retq
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95
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105 %b = load <2 x double>, <2 x double>* %a, align 16
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83
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106 %c = shufflevector <2 x double> %b, <2 x double> %b, <2 x i32> <i32 1, i32 0>
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107 %d = bitcast <2 x double> %c to <2 x i64>
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108 %e = extractelement <2 x i64> %d, i32 1
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109 ret i64 %e
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110 }
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111
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