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annotate lib/CodeGen/CalcSpillWeights.cpp @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===- CalcSpillWeights.cpp -----------------------------------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 #include "llvm/CodeGen/CalcSpillWeights.h"
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11 #include "llvm/ADT/SmallPtrSet.h"
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12 #include "llvm/CodeGen/LiveInterval.h"
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13 #include "llvm/CodeGen/LiveIntervals.h"
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14 #include "llvm/CodeGen/MachineFunction.h"
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15 #include "llvm/CodeGen/MachineInstr.h"
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16 #include "llvm/CodeGen/MachineLoopInfo.h"
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17 #include "llvm/CodeGen/MachineOperand.h"
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18 #include "llvm/CodeGen/MachineRegisterInfo.h"
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19 #include "llvm/CodeGen/TargetInstrInfo.h"
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20 #include "llvm/CodeGen/TargetRegisterInfo.h"
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21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
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22 #include "llvm/CodeGen/VirtRegMap.h"
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23 #include "llvm/Support/Debug.h"
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24 #include "llvm/Support/raw_ostream.h"
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25 #include <cassert>
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26 #include <tuple>
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27
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28 using namespace llvm;
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29
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30 #define DEBUG_TYPE "calcspillweights"
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31
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32 void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS,
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33 MachineFunction &MF,
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34 VirtRegMap *VRM,
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35 const MachineLoopInfo &MLI,
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36 const MachineBlockFrequencyInfo &MBFI,
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37 VirtRegAuxInfo::NormalizingFn norm) {
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38 DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
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39 << "********** Function: " << MF.getName() << '\n');
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40
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41 MachineRegisterInfo &MRI = MF.getRegInfo();
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42 VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm);
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43 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
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44 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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45 if (MRI.reg_nodbg_empty(Reg))
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46 continue;
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47 VRAI.calculateSpillWeightAndHint(LIS.getInterval(Reg));
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48 }
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49 }
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50
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51 // Return the preferred allocation register for reg, given a COPY instruction.
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52 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
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53 const TargetRegisterInfo &tri,
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54 const MachineRegisterInfo &mri) {
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55 unsigned sub, hreg, hsub;
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56 if (mi->getOperand(0).getReg() == reg) {
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57 sub = mi->getOperand(0).getSubReg();
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58 hreg = mi->getOperand(1).getReg();
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59 hsub = mi->getOperand(1).getSubReg();
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60 } else {
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61 sub = mi->getOperand(1).getSubReg();
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62 hreg = mi->getOperand(0).getReg();
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63 hsub = mi->getOperand(0).getSubReg();
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64 }
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65
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66 if (!hreg)
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67 return 0;
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68
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69 if (TargetRegisterInfo::isVirtualRegister(hreg))
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70 return sub == hsub ? hreg : 0;
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71
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72 const TargetRegisterClass *rc = mri.getRegClass(reg);
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73 if (!tri.enableMultipleCopyHints()) {
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74 // Only allow physreg hints in rc.
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75 if (sub == 0)
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76 return rc->contains(hreg) ? hreg : 0;
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77
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78 // reg:sub should match the physreg hreg.
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79 return tri.getMatchingSuperReg(hreg, sub, rc);
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80 }
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81
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82 unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
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83 if (rc->contains(CopiedPReg))
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84 return CopiedPReg;
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85
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86 // Check if reg:sub matches so that a super register could be hinted.
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87 if (sub)
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88 return tri.getMatchingSuperReg(CopiedPReg, sub, rc);
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89
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90 return 0;
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91 }
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92
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93 // Check if all values in LI are rematerializable
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94 static bool isRematerializable(const LiveInterval &LI,
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95 const LiveIntervals &LIS,
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96 VirtRegMap *VRM,
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97 const TargetInstrInfo &TII) {
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98 unsigned Reg = LI.reg;
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99 unsigned Original = VRM ? VRM->getOriginal(Reg) : 0;
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100 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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101 I != E; ++I) {
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102 const VNInfo *VNI = *I;
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103 if (VNI->isUnused())
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104 continue;
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105 if (VNI->isPHIDef())
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106 return false;
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107
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108 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
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109 assert(MI && "Dead valno in interval");
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110
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111 // Trace copies introduced by live range splitting. The inline
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112 // spiller can rematerialize through these copies, so the spill
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113 // weight must reflect this.
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114 if (VRM) {
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115 while (MI->isFullCopy()) {
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116 // The copy destination must match the interval register.
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117 if (MI->getOperand(0).getReg() != Reg)
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118 return false;
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119
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120 // Get the source register.
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121 Reg = MI->getOperand(1).getReg();
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122
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123 // If the original (pre-splitting) registers match this
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124 // copy came from a split.
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125 if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
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126 VRM->getOriginal(Reg) != Original)
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127 return false;
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128
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129 // Follow the copy live-in value.
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130 const LiveInterval &SrcLI = LIS.getInterval(Reg);
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131 LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
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132 VNI = SrcQ.valueIn();
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133 assert(VNI && "Copy from non-existing value");
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134 if (VNI->isPHIDef())
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135 return false;
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136 MI = LIS.getInstructionFromIndex(VNI->def);
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137 assert(MI && "Dead valno in interval");
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
138 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
139 }
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
140
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
141 if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
147 void VirtRegAuxInfo::calculateSpillWeightAndHint(LiveInterval &li) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
148 float weight = weightCalcHelper(li);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
149 // Check if unspillable.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
150 if (weight < 0)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
151 return;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
152 li.weight = weight;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
153 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
154
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
155 float VirtRegAuxInfo::futureWeight(LiveInterval &li, SlotIndex start,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
156 SlotIndex end) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
157 return weightCalcHelper(li, &start, &end);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
158 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
159
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
160 float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
161 SlotIndex *end) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 MachineRegisterInfo &mri = MF.getRegInfo();
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
163 const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
164 MachineBasicBlock *mbb = nullptr;
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
165 MachineLoop *loop = nullptr;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 bool isExiting = false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 float totalWeight = 0;
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
168 unsigned numInstr = 0; // Number of instructions using li
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 SmallPtrSet<MachineInstr*, 8> visited;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
170
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
171 std::pair<unsigned, unsigned> TargetHint = mri.getRegAllocationHint(li.reg);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 // Don't recompute spill weight for an unspillable register.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 bool Spillable = li.isSpillable();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
176 bool localSplitArtifact = start && end;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
177
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
178 // Do not update future local split artifacts.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
179 bool updateLI = !localSplitArtifact;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
180
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
181 if (localSplitArtifact) {
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
182 MachineBasicBlock *localMBB = LIS.getMBBFromIndex(*end);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
183 assert(localMBB == LIS.getMBBFromIndex(*start) &&
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
184 "start and end are expected to be in the same basic block");
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
185
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
186 // Local split artifact will have 2 additional copy instructions and they
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
187 // will be in the same BB.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
188 // localLI = COPY other
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
189 // ...
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
190 // other = COPY localLI
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
191 totalWeight += LiveIntervals::getSpillWeight(true, false, &MBFI, localMBB);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
192 totalWeight += LiveIntervals::getSpillWeight(false, true, &MBFI, localMBB);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
193
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
194 numInstr += 2;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
195 }
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
196
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
197 // CopyHint is a sortable hint derived from a COPY instruction.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
198 struct CopyHint {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
199 unsigned Reg;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
200 float Weight;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
201 bool IsPhys;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
202 unsigned HintOrder;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
203 CopyHint(unsigned R, float W, bool P, unsigned HR) :
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
204 Reg(R), Weight(W), IsPhys(P), HintOrder(HR) {}
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
205 bool operator<(const CopyHint &rhs) const {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
206 // Always prefer any physreg hint.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
207 if (IsPhys != rhs.IsPhys)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
208 return (IsPhys && !rhs.IsPhys);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
209 if (Weight != rhs.Weight)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
210 return (Weight > rhs.Weight);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
211
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
212 // This is just a temporary way to achive NFC for targets that don't
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
213 // enable multiple copy hints. HintOrder should be removed when all
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
214 // targets return true in enableMultipleCopyHints().
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
215 return (HintOrder < rhs.HintOrder);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
216
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
217 #if 0 // Should replace the HintOrder check, see above.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
218 // (just for the purpose of maintaining the set)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
219 return Reg < rhs.Reg;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
220 #endif
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
221 }
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
222 };
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
223 std::set<CopyHint> CopyHints;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
224
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
225 // Temporary: see comment for HintOrder above.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
226 unsigned CopyHintOrder = 0;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
227 for (MachineRegisterInfo::reg_instr_iterator
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
228 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
229 I != E; ) {
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
230 MachineInstr *mi = &*(I++);
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
231
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
232 // For local split artifacts, we are interested only in instructions between
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
233 // the expected start and end of the range.
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
234 SlotIndex si = LIS.getInstructionIndex(*mi);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
235 if (localSplitArtifact && ((si < *start) || (si > *end)))
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
236 continue;
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
237
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
238 numInstr++;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 continue;
83
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
241 if (!visited.insert(mi).second)
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 float weight = 1.0f;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 if (Spillable) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 // Get loop info for mi.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 if (mi->getParent() != mbb) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 mbb = mi->getParent();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 loop = Loops.getLoopFor(mbb);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 isExiting = loop ? loop->isLoopExiting(mbb) : false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 // Calculate instr weight.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 bool reads, writes;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
255 std::tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
256 weight = LiveIntervals::getSpillWeight(writes, reads, &MBFI, *mi);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
257
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 // Give extra weight to what looks like a loop induction variable update.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
260 weight *= 3;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
261
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 totalWeight += weight;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
264
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
265 // Get allocation hints from copies.
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
266 if (!mi->isCopy() ||
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
267 (TargetHint.first != 0 && !tri.enableMultipleCopyHints()))
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 continue;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 unsigned hint = copyHint(mi, li.reg, tri, mri);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
270 if (!hint)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 continue;
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
272 // Force hweight onto the stack so that x86 doesn't add hidden precision,
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
273 // making the comparison incorrectly pass (i.e., 1 > 1 == true??).
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
274 //
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
275 // FIXME: we probably shouldn't use floats at all.
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
276 volatile float hweight = Hint[hint] += weight;
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
277 if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint))
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
278 CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint),
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
279 (tri.enableMultipleCopyHints() ? hint : CopyHintOrder++)));
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
280 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
281
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 Hint.clear();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
283
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
284 // Pass all the sorted copy hints to mri.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
285 if (updateLI && CopyHints.size()) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
286 // Remove a generic hint if previously added by target.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
287 if (TargetHint.first == 0 && TargetHint.second)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
288 mri.clearSimpleHint(li.reg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
289
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
290 for (auto &Hint : CopyHints) {
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
291 if (TargetHint.first != 0 && Hint.Reg == TargetHint.second)
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
292 // Don't add again the target-type hint.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
293 continue;
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
294 mri.addRegAllocationHint(li.reg, Hint.Reg);
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
295 if (!tri.enableMultipleCopyHints())
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
296 break;
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
297 }
134
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
298
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
299 // Weakly boost the spill weight of hinted registers.
3a76565eade5 update 5.0.1
mir3636
parents: 121
diff changeset
300 totalWeight *= 1.01F;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
302
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 // If the live interval was already unspillable, leave it that way.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 if (!Spillable)
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
305 return -1.0;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
307 // Mark li as unspillable if all live ranges are tiny and the interval
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
308 // is not live at any reg mask. If the interval is live at a reg mask
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
309 // spilling may be required.
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
310 if (updateLI && li.isZeroLength(LIS.getSlotIndexes()) &&
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 95
diff changeset
311 !li.isLiveAtIndexes(LIS.getRegMaskSlots())) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 li.markNotSpillable();
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
313 return -1.0;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
315
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 // If all of the definitions of the interval are re-materializable,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 // it is a preferred candidate for spilling.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 // FIXME: this gets much more complicated once we support non-trivial
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 // re-materialization.
95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
diff changeset
320 if (isRematerializable(li, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 totalWeight *= 0.5F;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
322
121
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
323 if (localSplitArtifact)
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
324 return normalize(totalWeight, start->distance(*end), numInstr);
803732b1fca8 LLVM 5.0
kono
parents: 120
diff changeset
325 return normalize(totalWeight, li.getSize(), numInstr);
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 }