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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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77
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14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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16
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17 #include "SystemZ.h"
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18 #include "SystemZRegisterInfo.h"
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121
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19 #include "llvm/ADT/ArrayRef.h"
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20 #include "llvm/CodeGen/MachineBasicBlock.h"
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21 #include "llvm/CodeGen/MachineFunction.h"
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22 #include "llvm/CodeGen/MachineInstrBuilder.h"
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134
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23 #include "llvm/CodeGen/TargetInstrInfo.h"
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121
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24 #include <cstdint>
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25
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26 #define GET_INSTRINFO_HEADER
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27 #include "SystemZGenInstrInfo.inc"
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28
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29 namespace llvm {
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30
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121
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31 class SystemZSubtarget;
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32
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33 namespace SystemZII {
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34
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35 enum {
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36 // See comments in SystemZInstrFormats.td.
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37 SimpleBDXLoad = (1 << 0),
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38 SimpleBDXStore = (1 << 1),
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39 Has20BitOffset = (1 << 2),
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40 HasIndex = (1 << 3),
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41 Is128Bit = (1 << 4),
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42 AccessSizeMask = (31 << 5),
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43 AccessSizeShift = 5,
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44 CCValuesMask = (15 << 10),
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45 CCValuesShift = 10,
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46 CompareZeroCCMaskMask = (15 << 14),
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47 CompareZeroCCMaskShift = 14,
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48 CCMaskFirst = (1 << 18),
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49 CCMaskLast = (1 << 19),
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50 IsLogical = (1 << 20)
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51 };
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121
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52
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53 static inline unsigned getAccessSize(unsigned int Flags) {
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54 return (Flags & AccessSizeMask) >> AccessSizeShift;
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55 }
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56
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57 static inline unsigned getCCValues(unsigned int Flags) {
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58 return (Flags & CCValuesMask) >> CCValuesShift;
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59 }
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121
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60
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61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
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62 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
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63 }
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64
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65 // SystemZ MachineOperand target flags.
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66 enum {
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67 // Masks out the bits for the access model.
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68 MO_SYMBOL_MODIFIER = (3 << 0),
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69
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70 // @GOT (aka @GOTENT)
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71 MO_GOT = (1 << 0),
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72
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73 // @INDNTPOFF
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74 MO_INDNTPOFF = (2 << 0)
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77
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75 };
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121
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76
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77
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77 // Classifies a branch.
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78 enum BranchType {
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79 // An instruction that branches on the current value of CC.
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80 BranchNormal,
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81
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82 // An instruction that peforms a 32-bit signed comparison and branches
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83 // on the result.
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84 BranchC,
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85
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86 // An instruction that peforms a 32-bit unsigned comparison and branches
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87 // on the result.
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88 BranchCL,
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89
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90 // An instruction that peforms a 64-bit signed comparison and branches
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91 // on the result.
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92 BranchCG,
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93
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94 // An instruction that peforms a 64-bit unsigned comparison and branches
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95 // on the result.
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96 BranchCLG,
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97
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98 // An instruction that decrements a 32-bit register and branches if
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99 // the result is nonzero.
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100 BranchCT,
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101
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102 // An instruction that decrements a 64-bit register and branches if
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103 // the result is nonzero.
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104 BranchCTG
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105 };
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121
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106
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107 // Information about a branch instruction.
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108 struct Branch {
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109 // The type of the branch.
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110 BranchType Type;
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111
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112 // CCMASK_<N> is set if CC might be equal to N.
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113 unsigned CCValid;
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114
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115 // CCMASK_<N> is set if the branch should be taken when CC == N.
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116 unsigned CCMask;
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117
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118 // The target of the branch.
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119 const MachineOperand *Target;
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120
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121 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
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122 const MachineOperand *target)
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123 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
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124 };
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121
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125
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120
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126 // Kinds of fused compares in compare-and-* instructions. Together with type
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127 // of the converted compare, this identifies the compare-and-*
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128 // instruction.
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129 enum FusedCompareType {
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130 // Relative branch - CRJ etc.
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131 CompareAndBranch,
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132
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133 // Indirect branch, used for return - CRBReturn etc.
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134 CompareAndReturn,
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135
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136 // Indirect branch, used for sibcall - CRBCall etc.
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137 CompareAndSibcall,
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138
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139 // Trap
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140 CompareAndTrap
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141 };
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121
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142
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143 } // end namespace SystemZII
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144
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145 class SystemZInstrInfo : public SystemZGenInstrInfo {
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146 const SystemZRegisterInfo RI;
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147 SystemZSubtarget &STI;
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148
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149 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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150 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
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120
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151 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
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152 bool ConvertHigh) const;
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153 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
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154 unsigned LowOpcodeK, unsigned HighOpcode) const;
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120
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155 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
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156 unsigned HighOpcode) const;
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121
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157 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
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158 unsigned HighOpcode) const;
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159 void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
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160 unsigned HighOpcode) const;
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120
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161 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
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162 unsigned Size) const;
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120
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163 void expandLoadStackGuard(MachineInstr *MI) const;
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164
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165 MachineInstrBuilder
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166 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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167 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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168 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
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169 bool UndefSrc) const;
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170
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171 virtual void anchor();
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121
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172
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173 protected:
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174 /// Commutes the operands in the given instruction by changing the operands
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175 /// order and/or changing the instruction's opcode and/or the immediate value
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176 /// operand.
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177 ///
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178 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
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179 /// to be commuted.
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180 ///
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181 /// Do not call this method for a non-commutable instruction or
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182 /// non-commutable operands.
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183 /// Even though the instruction is commutable, the method may still
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184 /// fail to commute the operands, null pointer is returned in such cases.
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185 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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186 unsigned CommuteOpIdx1,
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187 unsigned CommuteOpIdx2) const override;
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188
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189 public:
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190 explicit SystemZInstrInfo(SystemZSubtarget &STI);
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191
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192 // Override TargetInstrInfo.
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120
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193 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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194 int &FrameIndex) const override;
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120
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195 unsigned isStoreToStackSlot(const MachineInstr &MI,
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196 int &FrameIndex) const override;
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120
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197 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
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77
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198 int &SrcFrameIndex) const override;
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120
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199 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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200 MachineBasicBlock *&FBB,
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201 SmallVectorImpl<MachineOperand> &Cond,
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202 bool AllowModify) const override;
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120
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203 unsigned removeBranch(MachineBasicBlock &MBB,
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204 int *BytesRemoved = nullptr) const override;
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205 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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206 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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120
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207 const DebugLoc &DL,
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208 int *BytesAdded = nullptr) const override;
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209 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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210 unsigned &SrcReg2, int &Mask, int &Value) const override;
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120
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211 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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212 unsigned SrcReg2, int Mask, int Value,
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213 const MachineRegisterInfo *MRI) const override;
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121
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214 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
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215 unsigned, unsigned, int&, int&, int&) const override;
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216 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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217 const DebugLoc &DL, unsigned DstReg,
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218 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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219 unsigned FalseReg) const override;
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220 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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221 MachineRegisterInfo *MRI) const override;
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222 bool isPredicable(const MachineInstr &MI) const override;
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223 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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224 unsigned ExtraPredCycles,
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225 BranchProbability Probability) const override;
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226 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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227 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
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228 MachineBasicBlock &FMBB,
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229 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
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230 BranchProbability Probability) const override;
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120
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231 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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232 BranchProbability Probability) const override;
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233 bool PredicateInstruction(MachineInstr &MI,
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95
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234 ArrayRef<MachineOperand> Pred) const override;
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77
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235 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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120
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236 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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77
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237 bool KillSrc) const override;
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238 void storeRegToStackSlot(MachineBasicBlock &MBB,
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239 MachineBasicBlock::iterator MBBI,
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240 unsigned SrcReg, bool isKill, int FrameIndex,
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241 const TargetRegisterClass *RC,
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242 const TargetRegisterInfo *TRI) const override;
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243 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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244 MachineBasicBlock::iterator MBBI,
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245 unsigned DestReg, int FrameIdx,
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246 const TargetRegisterClass *RC,
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247 const TargetRegisterInfo *TRI) const override;
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248 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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120
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249 MachineInstr &MI,
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250 LiveVariables *LV) const override;
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120
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251 MachineInstr *
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252 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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253 ArrayRef<unsigned> Ops,
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254 MachineBasicBlock::iterator InsertPt, int FrameIndex,
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255 LiveIntervals *LIS = nullptr) const override;
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256 MachineInstr *foldMemoryOperandImpl(
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257 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
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258 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
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259 LiveIntervals *LIS = nullptr) const override;
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260 bool expandPostRAPseudo(MachineInstr &MBBI) const override;
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261 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
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262 override;
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263
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264 // Return the SystemZRegisterInfo, which this class owns.
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265 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
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266
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267 // Return the size in bytes of MI.
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120
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268 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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269
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270 // Return true if MI is a conditional or unconditional branch.
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271 // When returning true, set Cond to the mask of condition-code
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272 // values on which the instruction will branch, and set Target
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273 // to the operand that contains the branch target. This target
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274 // can be a register or a basic block.
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120
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275 SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
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276
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277 // Get the load and store opcodes for a given register class.
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278 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
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279 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
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280
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281 // Opcode is the opcode of an instruction that has an address operand,
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282 // and the caller wants to perform that instruction's operation on an
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283 // address that has displacement Offset. Return the opcode of a suitable
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284 // instruction (which might be Opcode itself) or 0 if no such instruction
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285 // exists.
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286 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
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287
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288 // If Opcode is a load instruction that has a LOAD AND TEST form,
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289 // return the opcode for the testing form, otherwise return 0.
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290 unsigned getLoadAndTest(unsigned Opcode) const;
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291
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292 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
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293 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
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294 // significant. Set Start and End to the I3 and I4 operands if so.
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295 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
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296 unsigned &Start, unsigned &End) const;
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297
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298 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
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299 // operation exists, return the opcode for the latter, otherwise return 0.
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300 // MI, if nonnull, is the compare instruction.
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120
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301 unsigned getFusedCompare(unsigned Opcode,
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302 SystemZII::FusedCompareType Type,
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303 const MachineInstr *MI = nullptr) const;
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304
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121
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305 // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
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306 // operation exists, returh the opcode for the latter, otherwise return 0.
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307 unsigned getLoadAndTrap(unsigned Opcode) const;
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308
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309 // Emit code before MBBI in MI to move immediate value Value into
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310 // physical register Reg.
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311 void loadImmediate(MachineBasicBlock &MBB,
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312 MachineBasicBlock::iterator MBBI,
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313 unsigned Reg, uint64_t Value) const;
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120
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314
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315 // Sometimes, it is possible for the target to tell, even without
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316 // aliasing information, that two MIs access different memory
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317 // addresses. This function returns true if two MIs access different
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318 // memory addresses and false otherwise.
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319 bool
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320 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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321 AliasAnalysis *AA = nullptr) const override;
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322 };
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323
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324 } // end namespace llvm
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325
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326 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
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