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120
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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83
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2 ; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
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3
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4 define i64 @t0(x86_mmx* %p) {
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5 ; CHECK-LABEL: t0:
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134
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6 ; CHECK: ## %bb.0:
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120
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7 ; CHECK-NEXT: movq (%rdi), %mm0
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83
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8 ; CHECK-NEXT: paddq %mm0, %mm0
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134
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9 ; CHECK-NEXT: movq %mm0, %rax
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83
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10 ; CHECK-NEXT: retq
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95
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11 %t = load x86_mmx, x86_mmx* %p
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83
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12 %u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %t)
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13 %s = bitcast x86_mmx %u to i64
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14 ret i64 %s
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15 }
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16
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17 define i64 @t1(x86_mmx* %p) {
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18 ; CHECK-LABEL: t1:
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134
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19 ; CHECK: ## %bb.0:
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120
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20 ; CHECK-NEXT: movq (%rdi), %mm0
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83
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21 ; CHECK-NEXT: paddd %mm0, %mm0
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134
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22 ; CHECK-NEXT: movq %mm0, %rax
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83
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23 ; CHECK-NEXT: retq
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95
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24 %t = load x86_mmx, x86_mmx* %p
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83
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25 %u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %t)
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26 %s = bitcast x86_mmx %u to i64
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27 ret i64 %s
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28 }
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29
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30 define i64 @t2(x86_mmx* %p) {
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31 ; CHECK-LABEL: t2:
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134
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32 ; CHECK: ## %bb.0:
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120
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33 ; CHECK-NEXT: movq (%rdi), %mm0
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83
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34 ; CHECK-NEXT: paddw %mm0, %mm0
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134
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35 ; CHECK-NEXT: movq %mm0, %rax
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83
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36 ; CHECK-NEXT: retq
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95
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37 %t = load x86_mmx, x86_mmx* %p
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83
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38 %u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %t)
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39 %s = bitcast x86_mmx %u to i64
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40 ret i64 %s
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41 }
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42
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43 define i64 @t3(x86_mmx* %p) {
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44 ; CHECK-LABEL: t3:
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134
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45 ; CHECK: ## %bb.0:
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120
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46 ; CHECK-NEXT: movq (%rdi), %mm0
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83
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47 ; CHECK-NEXT: paddb %mm0, %mm0
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134
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48 ; CHECK-NEXT: movq %mm0, %rax
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83
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49 ; CHECK-NEXT: retq
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95
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50 %t = load x86_mmx, x86_mmx* %p
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83
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51 %u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %t)
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52 %s = bitcast x86_mmx %u to i64
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53 ret i64 %s
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54 }
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55
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56 @R = external global x86_mmx
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57
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58 define void @t4(<1 x i64> %A, <1 x i64> %B) {
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59 ; CHECK-LABEL: t4:
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134
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60 ; CHECK: ## %bb.0: ## %entry
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61 ; CHECK-NEXT: movq %rdi, %mm0
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62 ; CHECK-NEXT: movq %rsi, %mm1
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120
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63 ; CHECK-NEXT: paddusw %mm0, %mm1
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64 ; CHECK-NEXT: movq _R@{{.*}}(%rip), %rax
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65 ; CHECK-NEXT: movq %mm1, (%rax)
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66 ; CHECK-NEXT: emms
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67 ; CHECK-NEXT: retq
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83
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68 entry:
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69 %tmp2 = bitcast <1 x i64> %A to x86_mmx
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70 %tmp3 = bitcast <1 x i64> %B to x86_mmx
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71 %tmp7 = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %tmp2, x86_mmx %tmp3)
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72 store x86_mmx %tmp7, x86_mmx* @R
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73 tail call void @llvm.x86.mmx.emms()
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74 ret void
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75 }
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76
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77 define i64 @t5(i32 %a, i32 %b) nounwind readnone {
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78 ; CHECK-LABEL: t5:
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134
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79 ; CHECK: ## %bb.0:
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120
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80 ; CHECK-NEXT: movd %esi, %xmm0
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81 ; CHECK-NEXT: movd %edi, %xmm1
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83
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82 ; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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121
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83 ; CHECK-NEXT: movq %xmm1, %rax
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83
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84 ; CHECK-NEXT: retq
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85 %v0 = insertelement <2 x i32> undef, i32 %a, i32 0
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86 %v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
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87 %conv = bitcast <2 x i32> %v1 to i64
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88 ret i64 %conv
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89 }
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90
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91 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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92
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93 define <1 x i64> @t6(i64 %t) {
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94 ; CHECK-LABEL: t6:
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134
|
95 ; CHECK: ## %bb.0:
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96 ; CHECK-NEXT: movq %rdi, %mm0
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83
|
97 ; CHECK-NEXT: psllq $48, %mm0
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|
134
|
98 ; CHECK-NEXT: movq %mm0, %rax
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83
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99 ; CHECK-NEXT: retq
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100 %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
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101 %t0 = bitcast <1 x i64> %t1 to x86_mmx
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102 %t2 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %t0, i32 48)
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103 %t3 = bitcast x86_mmx %t2 to <1 x i64>
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104 ret <1 x i64> %t3
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105 }
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106
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107 declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx)
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108 declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
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109 declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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110 declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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111 declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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112 declare void @llvm.x86.mmx.emms()
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113
|
