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1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "MipsMachineFunction.h"
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77
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15 #include "Mips.h"
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16 #include "MipsRegisterInfo.h"
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17 #include "MipsSubtarget.h"
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18 #include "MipsTargetMachine.h"
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19 #include "llvm/IR/Attributes.h"
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20 #include "llvm/IR/Function.h"
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21 #include "llvm/Support/CommandLine.h"
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22 #include "llvm/Support/Debug.h"
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23 #include "llvm/Support/TargetRegistry.h"
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24 #include "llvm/Support/raw_ostream.h"
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25
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77
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26 using namespace llvm;
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27
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28 #define DEBUG_TYPE "mips-subtarget"
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29
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30 #define GET_SUBTARGETINFO_TARGET_DESC
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31 #define GET_SUBTARGETINFO_CTOR
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32 #include "MipsGenSubtargetInfo.inc"
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33
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34 // FIXME: Maybe this should be on by default when Mips16 is specified
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35 //
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36 static cl::opt<bool> Mixed16_32(
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37 "mips-mixed-16-32",
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38 cl::init(false),
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39 cl::desc("Allow for a mixture of Mips16 "
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40 "and Mips32 code in a single source file"),
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41 cl::Hidden);
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42
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43 static cl::opt<bool> Mips_Os16(
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44 "mips-os16",
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45 cl::init(false),
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46 cl::desc("Compile all functions that don' use "
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47 "floating point as Mips 16"),
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48 cl::Hidden);
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49
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50 static cl::opt<bool>
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51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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52 cl::desc("MIPS: mips16 hard float enable."),
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53 cl::init(false));
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54
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55 static cl::opt<bool>
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56 Mips16ConstantIslands(
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33
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57 "mips16-constant-islands", cl::NotHidden,
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58 cl::desc("MIPS: mips16 constant islands enable."),
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59 cl::init(true));
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60
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77
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61 /// Select the Mips CPU for the given triple and cpu name.
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62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
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63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
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64 if (CPU.empty() || CPU == "generic") {
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65 if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
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66 CPU = "mips32";
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67 else
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68 CPU = "mips64";
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69 }
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70 return CPU;
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71 }
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72
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73 void MipsSubtarget::anchor() { }
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74
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77
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75 static std::string computeDataLayout(const MipsSubtarget &ST) {
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76 std::string Ret = "";
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77
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78 // There are both little and big endian mips.
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79 if (ST.isLittle())
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80 Ret += "e";
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81 else
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82 Ret += "E";
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83
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84 Ret += "-m:m";
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85
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86 // Pointers are 32 bit on some ABIs.
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87 if (!ST.isABI_N64())
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88 Ret += "-p:32:32";
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89
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90 // 8 and 16 bit integers only need no have natural alignment, but try to
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91 // align them to 32 bits. 64 bit integers have natural alignment.
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92 Ret += "-i8:8:32-i16:16:32-i64:64";
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93
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94 // 32 bit registers are always available and the stack is at least 64 bit
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95 // aligned. On N64 64 bit registers are also available and the stack is
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96 // 128 bit aligned.
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97 if (ST.isABI_N64() || ST.isABI_N32())
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98 Ret += "-n32:64-S128";
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99 else
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100 Ret += "-n32-S64";
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101
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102 return Ret;
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103 }
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104
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105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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106 const std::string &FS, bool little,
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77
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107 MipsTargetMachine *_TM)
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108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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109 MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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110 IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
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111 IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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112 IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
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113 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
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114 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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115 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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116 AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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117 HasMSA(false), TM(_TM), TargetTriple(TT),
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118 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
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119 TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)),
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120 FrameLowering(MipsFrameLowering::create(*this)),
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121 TLInfo(MipsTargetLowering::create(*TM, *this)) {
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33
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122
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123 PreviousInMips16Mode = InMips16Mode;
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124
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125 // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
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126 // MIPS-V. They have not been tested and currently exist for the integrated
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127 // assembler only.
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128 if (MipsArchVersion == Mips1)
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129 report_fatal_error("Code generation for MIPS-I is not implemented", false);
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130 if (MipsArchVersion == Mips2)
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131 report_fatal_error("Code generation for MIPS-II is not implemented", false);
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132 if (MipsArchVersion == Mips3)
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133 report_fatal_error("Code generation for MIPS-III is not implemented",
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134 false);
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135 if (MipsArchVersion == Mips5)
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136 report_fatal_error("Code generation for MIPS-V is not implemented", false);
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137
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138 // Assert exactly one ABI was chosen.
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139 assert(MipsABI != UnknownABI);
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140 assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
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141 ((getFeatureBits() & Mips::FeatureEABI) != 0) +
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142 ((getFeatureBits() & Mips::FeatureN32) != 0) +
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143 ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
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144
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145 // Check if Architecture and ABI are compatible.
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77
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146 assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
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147 (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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148 "Invalid Arch & ABI pair.");
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149
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150 if (hasMSA() && !isFP64bit())
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151 report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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152 "See -mattr=+fp64.",
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153 false);
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154
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155 if (!isABI_O32() && !useOddSPReg())
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156 report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
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157
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158 if (IsFPXX && (isABI_N32() || isABI_N64()))
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159 report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
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160
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161 if (hasMips32r6()) {
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162 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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163
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164 assert(isFP64bit());
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165 assert(isNaN2008());
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166 if (hasDSP())
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167 report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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168 }
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169
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170 // Is the target system Linux ?
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171 if (TT.find("linux") == std::string::npos)
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172 IsLinux = false;
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173
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174 // Set UseSmallSection.
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77
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175 // TODO: Investigate the IsLinux check. I suspect it's really checking for
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176 // bare-metal.
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177 UseSmallSection = !IsLinux && (TM->getRelocationModel() == Reloc::Static);
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178 }
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179
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77
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180 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
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181 bool MipsSubtarget::enablePostMachineScheduler() const { return true; }
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182
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183 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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184 CriticalPathRCs.clear();
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77
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185 CriticalPathRCs.push_back(isGP64bit() ?
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186 &Mips::GPR64RegClass : &Mips::GPR32RegClass);
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77
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187 }
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188
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189 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
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190 return CodeGenOpt::Aggressive;
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191 }
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192
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77
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193 MipsSubtarget &
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194 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
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195 const TargetMachine *TM) {
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196 std::string CPUName = selectMipsCPU(TargetTriple, CPU);
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197
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198 // Parse features string.
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199 ParseSubtargetFeatures(CPUName, FS);
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200 // Initialize scheduling itinerary for the specified CPU.
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201 InstrItins = getInstrItineraryForCPU(CPUName);
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202
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203 if (InMips16Mode && !TM->Options.UseSoftFloat)
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204 InMips16HardFloat = true;
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205
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206 return *this;
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207 }
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208
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77
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209 bool MipsSubtarget::abiUsesSoftFloat() const {
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210 return TM->Options.UseSoftFloat && !InMips16HardFloat;
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211 }
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212
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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213 bool MipsSubtarget::useConstantIslands() {
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214 DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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215 return Mips16ConstantIslands;
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216 }
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77
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217
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218 Reloc::Model MipsSubtarget::getRelocationModel() const {
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219 return TM->getRelocationModel();
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220 }
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