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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Implements the info about Mips target spec.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "MipsTargetMachine.h"
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15 #include "Mips.h"
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77
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16 #include "Mips16FrameLowering.h"
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|
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17 #include "Mips16ISelDAGToDAG.h"
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18 #include "Mips16ISelLowering.h"
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|
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19 #include "Mips16InstrInfo.h"
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20 #include "MipsFrameLowering.h"
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21 #include "MipsInstrInfo.h"
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22 #include "MipsSEFrameLowering.h"
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77
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23 #include "MipsSEISelDAGToDAG.h"
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24 #include "MipsSEISelLowering.h"
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77
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25 #include "MipsSEInstrInfo.h"
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83
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26 #include "MipsTargetObjectFile.h"
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27 #include "llvm/Analysis/TargetTransformInfo.h"
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28 #include "llvm/CodeGen/Passes.h"
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83
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29 #include "llvm/IR/LegacyPassManager.h"
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30 #include "llvm/Support/Debug.h"
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77
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31 #include "llvm/Support/TargetRegistry.h"
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32 #include "llvm/Support/raw_ostream.h"
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33 #include "llvm/Transforms/Scalar.h"
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95
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34
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35 using namespace llvm;
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36
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37 #define DEBUG_TYPE "mips"
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38
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39 extern "C" void LLVMInitializeMipsTarget() {
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40 // Register the target.
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41 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
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42 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
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43 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
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44 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
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45 }
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46
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95
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47 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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48 const TargetOptions &Options,
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49 bool isLittle) {
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50 std::string Ret = "";
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95
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51 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
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52
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53 // There are both little and big endian mips.
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54 if (isLittle)
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55 Ret += "e";
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56 else
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57 Ret += "E";
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58
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59 Ret += "-m:m";
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60
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61 // Pointers are 32 bit on some ABIs.
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62 if (!ABI.IsN64())
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63 Ret += "-p:32:32";
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64
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65 // 8 and 16 bit integers only need to have natural alignment, but try to
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83
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66 // align them to 32 bits. 64 bit integers have natural alignment.
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67 Ret += "-i8:8:32-i16:16:32-i64:64";
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68
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69 // 32 bit registers are always available and the stack is at least 64 bit
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70 // aligned. On N64 64 bit registers are also available and the stack is
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71 // 128 bit aligned.
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72 if (ABI.IsN64() || ABI.IsN32())
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73 Ret += "-n32:64-S128";
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74 else
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75 Ret += "-n32-S64";
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76
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77 return Ret;
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78 }
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79
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80 // On function prologue, the stack is created by decrementing
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81 // its pointer. Once decremented, all references are done with positive
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82 // offset from the stack/frame pointer, using StackGrowsUp enables
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83 // an easier handling.
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84 // Using CodeModel::Large enables different CALL behavior.
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95
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85 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
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77
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86 StringRef CPU, StringRef FS,
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87 const TargetOptions &Options,
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88 Reloc::Model RM, CodeModel::Model CM,
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89 CodeGenOpt::Level OL, bool isLittle)
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95
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90 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
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91 CPU, FS, Options, RM, CM, OL),
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83
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92 isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
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95
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93 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
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94 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
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77
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95 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
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96 isLittle, *this),
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97 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
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98 isLittle, *this) {
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99 Subtarget = &DefaultSubtarget;
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100 initAsmInfo();
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101 }
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102
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103 MipsTargetMachine::~MipsTargetMachine() {}
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104
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105 void MipsebTargetMachine::anchor() { }
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106
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107 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
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108 StringRef CPU, StringRef FS,
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109 const TargetOptions &Options,
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110 Reloc::Model RM, CodeModel::Model CM,
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111 CodeGenOpt::Level OL)
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112 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
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113
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114 void MipselTargetMachine::anchor() { }
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115
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116 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
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117 StringRef CPU, StringRef FS,
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118 const TargetOptions &Options,
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119 Reloc::Model RM, CodeModel::Model CM,
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120 CodeGenOpt::Level OL)
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121 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
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122
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123 const MipsSubtarget *
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124 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
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125 Attribute CPUAttr = F.getFnAttribute("target-cpu");
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126 Attribute FSAttr = F.getFnAttribute("target-features");
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127
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128 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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129 ? CPUAttr.getValueAsString().str()
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130 : TargetCPU;
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131 std::string FS = !FSAttr.hasAttribute(Attribute::None)
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132 ? FSAttr.getValueAsString().str()
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133 : TargetFS;
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134 bool hasMips16Attr =
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135 !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
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136 bool hasNoMips16Attr =
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137 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
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138
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139 // FIXME: This is related to the code below to reset the target options,
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140 // we need to know whether or not the soft float flag is set on the
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95
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141 // function, so we can enable it as a subtarget feature.
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142 bool softFloat =
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143 F.hasFnAttribute("use-soft-float") &&
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144 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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83
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145
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146 if (hasMips16Attr)
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147 FS += FS.empty() ? "+mips16" : ",+mips16";
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148 else if (hasNoMips16Attr)
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149 FS += FS.empty() ? "-mips16" : ",-mips16";
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150 if (softFloat)
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151 FS += FS.empty() ? "+soft-float" : ",+soft-float";
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83
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152
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153 auto &I = SubtargetMap[CPU + FS];
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83
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154 if (!I) {
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155 // This needs to be done before we create a new subtarget since any
|
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156 // creation will depend on the TM and the code generation flags on the
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157 // function that reside in TargetOptions.
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158 resetTargetOptions(F);
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95
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159 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
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160 *this);
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83
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161 }
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162 return I.get();
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163 }
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164
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165 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
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166 DEBUG(dbgs() << "resetSubtarget\n");
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83
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167
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168 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
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169 MF->setSubtarget(Subtarget);
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170 return;
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171 }
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172
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173 namespace {
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174 /// Mips Code Generator Pass Configuration Options.
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175 class MipsPassConfig : public TargetPassConfig {
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176 public:
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177 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
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178 : TargetPassConfig(TM, PM) {
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179 // The current implementation of long branch pass requires a scratch
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180 // register ($at) to be available before branch instructions. Tail merging
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181 // can break this requirement, so disable it when long branch pass is
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182 // enabled.
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183 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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184 }
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185
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186 MipsTargetMachine &getMipsTargetMachine() const {
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187 return getTM<MipsTargetMachine>();
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188 }
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189
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190 const MipsSubtarget &getMipsSubtarget() const {
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191 return *getMipsTargetMachine().getSubtargetImpl();
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192 }
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193
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194 void addIRPasses() override;
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195 bool addInstSelector() override;
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196 void addMachineSSAOptimization() override;
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83
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197 void addPreEmitPass() override;
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77
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198
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83
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199 void addPreRegAlloc() override;
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200
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201 };
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202 } // namespace
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203
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204 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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205 return new MipsPassConfig(this, PM);
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206 }
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207
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208 void MipsPassConfig::addIRPasses() {
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209 TargetPassConfig::addIRPasses();
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83
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210 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
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211 if (getMipsSubtarget().os16())
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212 addPass(createMipsOs16Pass(getMipsTargetMachine()));
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213 if (getMipsSubtarget().inMips16HardFloat())
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95
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214 addPass(createMips16HardFloatPass(getMipsTargetMachine()));
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215 }
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216 // Install an instruction selector pass using
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217 // the ISelDag to gen Mips code.
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218 bool MipsPassConfig::addInstSelector() {
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|
95
|
219 addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
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77
|
220 addPass(createMips16ISelDag(getMipsTargetMachine()));
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|
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221 addPass(createMipsSEISelDag(getMipsTargetMachine()));
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222 return false;
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223 }
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224
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33
|
225 void MipsPassConfig::addMachineSSAOptimization() {
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|
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226 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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|
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227 TargetPassConfig::addMachineSSAOptimization();
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|
|
228 }
|
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229
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83
|
230 void MipsPassConfig::addPreRegAlloc() {
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231 if (getOptLevel() == CodeGenOpt::None)
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77
|
232 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
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|
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233 }
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234
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83
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235 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
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95
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236 return TargetIRAnalysis([this](const Function &F) {
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83
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237 if (Subtarget->allowMixed16_32()) {
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238 DEBUG(errs() << "No Target Transform Info Pass Added\n");
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239 // FIXME: This is no longer necessary as the TTI returned is per-function.
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95
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240 return TargetTransformInfo(F.getParent()->getDataLayout());
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83
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241 }
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242
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243 DEBUG(errs() << "Target Transform Info Pass Added\n");
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244 return TargetTransformInfo(BasicTTIImpl(this, F));
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245 });
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246 }
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247
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248 // Implemented by targets that want to run passes immediately before
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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249 // machine code is emitted. return true if -print-machineinstrs should
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250 // print out the code after the passes.
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83
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251 void MipsPassConfig::addPreEmitPass() {
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252 MipsTargetMachine &TM = getMipsTargetMachine();
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253 addPass(createMipsDelaySlotFillerPass(TM));
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77
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254 addPass(createMipsLongBranchPass(TM));
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255 addPass(createMipsConstantIslandPass(TM));
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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256 }
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