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annotate lib/Target/Sparc/SparcISelLowering.h @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
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11 // selection DAG.
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12 //
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13 //===----------------------------------------------------------------------===//
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15 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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16 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
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17
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18 #include "Sparc.h"
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19 #include "llvm/Target/TargetLowering.h"
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20
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21 namespace llvm {
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22 class SparcSubtarget;
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23
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24 namespace SPISD {
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25 enum NodeType : unsigned {
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26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
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27 CMPICC, // Compare two GPR operands, set icc+xcc.
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28 CMPFCC, // Compare two FP operands, set fcc.
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29 BRICC, // Branch to dest on icc condition
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30 BRXCC, // Branch to dest on xcc condition (64-bit only).
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31 BRFCC, // Branch to dest on fcc condition
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32 SELECT_ICC, // Select between two values using the current ICC flags.
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33 SELECT_XCC, // Select between two values using the current XCC flags.
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34 SELECT_FCC, // Select between two values using the current FCC flags.
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35
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36 Hi, Lo, // Hi/Lo operations, typically on a global address.
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37
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38 FTOI, // FP to Int within a FP register.
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39 ITOF, // Int to FP within a FP register.
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40 FTOX, // FP to Int64 within a FP register.
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41 XTOF, // Int64 to FP within a FP register.
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42
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43 CALL, // A call instruction.
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44 RET_FLAG, // Return with a flag operand.
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45 GLOBAL_BASE_REG, // Global base reg for PIC.
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46 FLUSHW, // FLUSH register windows to stack.
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47
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48 TLS_ADD, // For Thread Local Storage (TLS).
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49 TLS_LD,
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50 TLS_CALL
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51 };
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52 }
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53
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54 class SparcTargetLowering : public TargetLowering {
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55 const SparcSubtarget *Subtarget;
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56 public:
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57 SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI);
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58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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59
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60 /// computeKnownBitsForTargetNode - Determine which of the bits specified
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61 /// in Mask are known to be either zero or one and return them in the
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62 /// KnownZero/KnownOne bitsets.
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63 void computeKnownBitsForTargetNode(const SDValue Op,
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64 APInt &KnownZero,
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65 APInt &KnownOne,
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66 const SelectionDAG &DAG,
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67 unsigned Depth = 0) const override;
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68
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69 MachineBasicBlock *
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70 EmitInstrWithCustomInserter(MachineInstr *MI,
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71 MachineBasicBlock *MBB) const override;
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72
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73 const char *getTargetNodeName(unsigned Opcode) const override;
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74
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75 ConstraintType getConstraintType(StringRef Constraint) const override;
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76 ConstraintWeight
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77 getSingleConstraintMatchWeight(AsmOperandInfo &info,
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78 const char *constraint) const override;
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79 void LowerAsmOperandForConstraint(SDValue Op,
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80 std::string &Constraint,
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81 std::vector<SDValue> &Ops,
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82 SelectionDAG &DAG) const override;
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83 std::pair<unsigned, const TargetRegisterClass *>
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84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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85 StringRef Constraint, MVT VT) const override;
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86
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87 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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88 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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89 return MVT::i32;
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90 }
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91
100
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92 /// If a physical register, this returns the register that receives the
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93 /// exception address on entry to an EH pad.
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94 unsigned
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95 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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96 return SP::I0;
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97 }
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98
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99 /// If a physical register, this returns the register that receives the
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100 /// exception typeid on entry to a landing pad.
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101 unsigned
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102 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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103 return SP::I1;
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104 }
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105
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106 /// getSetCCResultType - Return the ISD::SETCC ValueType
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107 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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108 EVT VT) const override;
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109
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110 SDValue
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111 LowerFormalArguments(SDValue Chain,
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112 CallingConv::ID CallConv,
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113 bool isVarArg,
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114 const SmallVectorImpl<ISD::InputArg> &Ins,
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115 SDLoc dl, SelectionDAG &DAG,
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116 SmallVectorImpl<SDValue> &InVals) const override;
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117 SDValue LowerFormalArguments_32(SDValue Chain,
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118 CallingConv::ID CallConv,
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119 bool isVarArg,
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120 const SmallVectorImpl<ISD::InputArg> &Ins,
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121 SDLoc dl, SelectionDAG &DAG,
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122 SmallVectorImpl<SDValue> &InVals) const;
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123 SDValue LowerFormalArguments_64(SDValue Chain,
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124 CallingConv::ID CallConv,
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125 bool isVarArg,
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126 const SmallVectorImpl<ISD::InputArg> &Ins,
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127 SDLoc dl, SelectionDAG &DAG,
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128 SmallVectorImpl<SDValue> &InVals) const;
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129
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130 SDValue
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131 LowerCall(TargetLowering::CallLoweringInfo &CLI,
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132 SmallVectorImpl<SDValue> &InVals) const override;
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133 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
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134 SmallVectorImpl<SDValue> &InVals) const;
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135 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
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136 SmallVectorImpl<SDValue> &InVals) const;
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137
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138 SDValue
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139 LowerReturn(SDValue Chain,
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140 CallingConv::ID CallConv, bool isVarArg,
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141 const SmallVectorImpl<ISD::OutputArg> &Outs,
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142 const SmallVectorImpl<SDValue> &OutVals,
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143 SDLoc dl, SelectionDAG &DAG) const override;
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144 SDValue LowerReturn_32(SDValue Chain,
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145 CallingConv::ID CallConv, bool IsVarArg,
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146 const SmallVectorImpl<ISD::OutputArg> &Outs,
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147 const SmallVectorImpl<SDValue> &OutVals,
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148 SDLoc DL, SelectionDAG &DAG) const;
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149 SDValue LowerReturn_64(SDValue Chain,
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150 CallingConv::ID CallConv, bool IsVarArg,
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151 const SmallVectorImpl<ISD::OutputArg> &Outs,
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152 const SmallVectorImpl<SDValue> &OutVals,
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153 SDLoc DL, SelectionDAG &DAG) const;
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154
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155 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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156 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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157 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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158 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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159
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160 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
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161 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
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162 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
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163 SelectionDAG &DAG) const;
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164 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
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165
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166 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
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167 SDValue Arg, SDLoc DL,
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168 SelectionDAG &DAG) const;
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169 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
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170 const char *LibFuncName,
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171 unsigned numArgs) const;
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172 SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
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173 unsigned &SPCC,
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174 SDLoc DL,
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175 SelectionDAG &DAG) const;
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176
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177 bool ShouldShrinkFPConstant(EVT VT) const override {
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178 // Do not shrink FP constpool if VT == MVT::f128.
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179 // (ldd, call _Q_fdtoq) is more expensive than two ldds.
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180 return VT != MVT::f128;
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181 }
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182
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183 void ReplaceNodeResults(SDNode *N,
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184 SmallVectorImpl<SDValue>& Results,
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185 SelectionDAG &DAG) const override;
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186
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187 MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
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188 unsigned BROpcode) const;
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189 MachineBasicBlock *expandAtomicRMW(MachineInstr *MI,
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190 MachineBasicBlock *BB,
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191 unsigned Opcode,
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192 unsigned CondCode = 0) const;
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193 };
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194 } // end namespace llvm
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195
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196 #endif // SPARC_ISELLOWERING_H