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annotate test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
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2 ;REQUIRES: asserts
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3
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4 define void @main() {
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5 main_body:
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6 %0 = load <4 x float>, <4 x float> addrspace(9)* null
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7 %1 = extractelement <4 x float> %0, i32 3
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8 %2 = fptosi float %1 to i32
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9 %3 = bitcast i32 %2 to float
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10 %4 = bitcast float %3 to i32
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11 %5 = sdiv i32 %4, 4
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12 %6 = bitcast i32 %5 to float
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13 %7 = bitcast float %6 to i32
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14 %8 = mul i32 %7, 4
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15 %9 = bitcast i32 %8 to float
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16 %10 = bitcast float %9 to i32
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17 %11 = sub i32 0, %10
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18 %12 = bitcast i32 %11 to float
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19 %13 = bitcast float %3 to i32
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20 %14 = bitcast float %12 to i32
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21 %15 = add i32 %13, %14
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22 %16 = bitcast i32 %15 to float
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23 %17 = load <4 x float>, <4 x float> addrspace(9)* null
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24 %18 = extractelement <4 x float> %17, i32 0
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25 %19 = load <4 x float>, <4 x float> addrspace(9)* null
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26 %20 = extractelement <4 x float> %19, i32 1
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27 %21 = load <4 x float>, <4 x float> addrspace(9)* null
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28 %22 = extractelement <4 x float> %21, i32 2
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29 br label %LOOP
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30
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31 LOOP: ; preds = %IF31, %main_body
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32 %temp12.0 = phi float [ 0.000000e+00, %main_body ], [ %47, %IF31 ]
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33 %temp6.0 = phi float [ %22, %main_body ], [ %temp6.1, %IF31 ]
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34 %temp5.0 = phi float [ %20, %main_body ], [ %temp5.1, %IF31 ]
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35 %temp4.0 = phi float [ %18, %main_body ], [ %temp4.1, %IF31 ]
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36 %23 = bitcast float %temp12.0 to i32
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37 %24 = bitcast float %6 to i32
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38 %25 = icmp sge i32 %23, %24
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39 %26 = sext i1 %25 to i32
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40 %27 = bitcast i32 %26 to float
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41 %28 = bitcast float %27 to i32
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42 %29 = icmp ne i32 %28, 0
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43 br i1 %29, label %IF, label %LOOP29
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44
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45 IF: ; preds = %LOOP
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46 %30 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00)
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47 %31 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00)
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48 %32 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00)
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49 %33 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00)
95
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50 %34 = insertelement <4 x float> undef, float %30, i32 0
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51 %35 = insertelement <4 x float> %34, float %31, i32 1
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52 %36 = insertelement <4 x float> %35, float %32, i32 2
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53 %37 = insertelement <4 x float> %36, float %33, i32 3
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54 call void @llvm.R600.store.swizzle(<4 x float> %37, i32 0, i32 0)
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55 ret void
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56
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57 LOOP29: ; preds = %LOOP, %ENDIF30
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58 %temp6.1 = phi float [ %temp4.1, %ENDIF30 ], [ %temp6.0, %LOOP ]
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59 %temp5.1 = phi float [ %temp6.1, %ENDIF30 ], [ %temp5.0, %LOOP ]
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60 %temp4.1 = phi float [ %temp5.1, %ENDIF30 ], [ %temp4.0, %LOOP ]
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61 %temp20.0 = phi float [ %50, %ENDIF30 ], [ 0.000000e+00, %LOOP ]
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62 %38 = bitcast float %temp20.0 to i32
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63 %39 = bitcast float %16 to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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64 %40 = icmp sge i32 %38, %39
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65 %41 = sext i1 %40 to i32
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66 %42 = bitcast i32 %41 to float
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67 %43 = bitcast float %42 to i32
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68 %44 = icmp ne i32 %43, 0
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69 br i1 %44, label %IF31, label %ENDIF30
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70
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71 IF31: ; preds = %LOOP29
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72 %45 = bitcast float %temp12.0 to i32
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73 %46 = add i32 %45, 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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74 %47 = bitcast i32 %46 to float
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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75 br label %LOOP
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76
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77 ENDIF30: ; preds = %LOOP29
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78 %48 = bitcast float %temp20.0 to i32
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79 %49 = add i32 %48, 1
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80 %50 = bitcast i32 %49 to float
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81 br label %LOOP29
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82 }
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83
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84 declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
95
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85
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86 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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87
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88 attributes #0 = { readnone }