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annotate lib/Target/Mips/Mips16InstrInfo.h @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 1172e4bd9c6f
children c2174574ed3a
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1 //===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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15 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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16
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17 #include "Mips16RegisterInfo.h"
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18 #include "MipsInstrInfo.h"
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19 #include "llvm/CodeGen/MachineBasicBlock.h"
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20 #include "llvm/Support/MathExtras.h"
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21 #include <cstdint>
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22
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23 namespace llvm {
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24
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25 class MCInstrDesc;
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26 class MipsSubtarget;
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27
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28 class Mips16InstrInfo : public MipsInstrInfo {
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29 const Mips16RegisterInfo RI;
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30
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31 public:
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32 explicit Mips16InstrInfo(const MipsSubtarget &STI);
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34 const MipsRegisterInfo &getRegisterInfo() const override;
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35
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36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
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37 /// load from a stack slot, return the virtual or physical register number of
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38 /// the destination along with the FrameIndex of the loaded stack slot. If
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39 /// not, return 0. This predicate must return 0 if the instruction has
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40 /// any side effects other than loading from the stack slot.
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41 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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42 int &FrameIndex) const override;
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43
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44 /// isStoreToStackSlot - If the specified machine instruction is a direct
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45 /// store to a stack slot, return the virtual or physical register number of
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46 /// the source reg along with the FrameIndex of the loaded stack slot. If
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47 /// not, return 0. This predicate must return 0 if the instruction has
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48 /// any side effects other than storing to the stack slot.
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49 unsigned isStoreToStackSlot(const MachineInstr &MI,
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50 int &FrameIndex) const override;
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51
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52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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53 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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54 bool KillSrc) const override;
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55
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56 void storeRegToStack(MachineBasicBlock &MBB,
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57 MachineBasicBlock::iterator MBBI,
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58 unsigned SrcReg, bool isKill, int FrameIndex,
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59 const TargetRegisterClass *RC,
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60 const TargetRegisterInfo *TRI,
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61 int64_t Offset) const override;
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63 void loadRegFromStack(MachineBasicBlock &MBB,
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64 MachineBasicBlock::iterator MBBI,
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65 unsigned DestReg, int FrameIndex,
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66 const TargetRegisterClass *RC,
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67 const TargetRegisterInfo *TRI,
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68 int64_t Offset) const override;
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69
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70 bool expandPostRAPseudo(MachineInstr &MI) const override;
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71
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72 unsigned getOppositeBranchOpc(unsigned Opc) const override;
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73
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74 // Adjust SP by FrameSize bytes. Save RA, S0, S1
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75 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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76 MachineBasicBlock::iterator I) const;
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78 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
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79 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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80 MachineBasicBlock::iterator I) const;
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81
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82 /// Adjust SP by Amount bytes.
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83 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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84 MachineBasicBlock::iterator I) const override;
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85
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86 /// Emit a series of instructions to load an immediate.
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87 // This is to adjust some FrameReg. We return the new register to be used
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88 // in place of FrameReg and the adjusted immediate field (&NewImm)
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89 unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
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90 MachineBasicBlock::iterator II, const DebugLoc &DL,
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91 unsigned &NewImm) const;
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92
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93 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
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94
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95 static bool validSpImm8(int offset) {
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96 return ((offset & 7) == 0) && isInt<11>(offset);
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97 }
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98
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99 // build the proper one based on the Imm field
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100
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101 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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102
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103 void BuildAddiuSpImm
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104 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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105 private:
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106 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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107
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108 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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109 unsigned Opc) const;
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110
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111 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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112 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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113 MachineBasicBlock::iterator I,
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114 unsigned Reg1, unsigned Reg2) const;
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115
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116 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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117 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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118 MachineBasicBlock &MBB,
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119 MachineBasicBlock::iterator I) const;
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120 };
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122 } // end namespace llvm
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124 #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H