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120
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
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3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2
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4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
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5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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6
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77
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7 ; FNEG is defined as subtraction from -0.0.
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8
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9 ; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed.
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120
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10 define <4 x float> @t1(<4 x float> %Q) nounwind {
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11 ; X32-SSE-LABEL: t1:
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12 ; X32-SSE: # BB#0:
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121
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13 ; X32-SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0
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120
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14 ; X32-SSE-NEXT: retl
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15 ;
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16 ; X64-SSE-LABEL: t1:
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17 ; X64-SSE: # BB#0:
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18 ; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
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19 ; X64-SSE-NEXT: retq
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20 %tmp = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %Q
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21 ret <4 x float> %tmp
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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22 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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23
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77
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24 ; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg.
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120
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25 define <4 x float> @t2(<4 x float> %Q) nounwind {
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26 ; X32-SSE-LABEL: t2:
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27 ; X32-SSE: # BB#0:
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28 ; X32-SSE-NEXT: xorps %xmm1, %xmm1
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29 ; X32-SSE-NEXT: subps %xmm0, %xmm1
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30 ; X32-SSE-NEXT: movaps %xmm1, %xmm0
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31 ; X32-SSE-NEXT: retl
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32 ;
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33 ; X64-SSE-LABEL: t2:
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34 ; X64-SSE: # BB#0:
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35 ; X64-SSE-NEXT: xorps %xmm1, %xmm1
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36 ; X64-SSE-NEXT: subps %xmm0, %xmm1
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37 ; X64-SSE-NEXT: movaps %xmm1, %xmm0
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38 ; X64-SSE-NEXT: retq
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39 %tmp = fsub <4 x float> zeroinitializer, %Q
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40 ret <4 x float> %tmp
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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41 }
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77
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42
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43 ; If we're bitcasting an integer to an FP vector, we should avoid the FPU/vector unit entirely.
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44 ; Make sure that we're flipping the sign bit and only the sign bit of each float.
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45 ; So instead of something like this:
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46 ; movd %rdi, %xmm0
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47 ; xorps .LCPI2_0(%rip), %xmm0
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48 ;
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49 ; We should generate:
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50 ; movabsq (put sign bit mask in integer register))
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51 ; xorq (flip sign bits)
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120
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52 ; movd (move to xmm return register)
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77
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53
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120
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54 define <2 x float> @fneg_bitcast(i64 %i) nounwind {
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55 ; X32-SSE1-LABEL: fneg_bitcast:
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56 ; X32-SSE1: # BB#0:
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57 ; X32-SSE1-NEXT: pushl %ebp
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58 ; X32-SSE1-NEXT: movl %esp, %ebp
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59 ; X32-SSE1-NEXT: andl $-16, %esp
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60 ; X32-SSE1-NEXT: subl $32, %esp
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61 ; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
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62 ; X32-SSE1-NEXT: movl 12(%ebp), %ecx
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63 ; X32-SSE1-NEXT: xorl %eax, %ecx
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64 ; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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65 ; X32-SSE1-NEXT: xorl 8(%ebp), %eax
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66 ; X32-SSE1-NEXT: movl %eax, (%esp)
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67 ; X32-SSE1-NEXT: movaps (%esp), %xmm0
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68 ; X32-SSE1-NEXT: movl %ebp, %esp
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69 ; X32-SSE1-NEXT: popl %ebp
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70 ; X32-SSE1-NEXT: retl
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71 ;
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72 ; X32-SSE2-LABEL: fneg_bitcast:
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73 ; X32-SSE2: # BB#0:
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74 ; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
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75 ; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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76 ; X32-SSE2-NEXT: xorl %eax, %ecx
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77 ; X32-SSE2-NEXT: movd %ecx, %xmm1
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78 ; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax
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79 ; X32-SSE2-NEXT: movd %eax, %xmm0
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80 ; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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81 ; X32-SSE2-NEXT: retl
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82 ;
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83 ; X64-SSE1-LABEL: fneg_bitcast:
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84 ; X64-SSE1: # BB#0:
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85 ; X64-SSE1-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000
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86 ; X64-SSE1-NEXT: xorq %rdi, %rax
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87 ; X64-SSE1-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
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88 ; X64-SSE1-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
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89 ; X64-SSE1-NEXT: retq
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90 ;
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91 ; X64-SSE2-LABEL: fneg_bitcast:
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92 ; X64-SSE2: # BB#0:
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93 ; X64-SSE2-NEXT: movabsq $-9223372034707292160, %rax # imm = 0x8000000080000000
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94 ; X64-SSE2-NEXT: xorq %rdi, %rax
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121
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95 ; X64-SSE2-NEXT: movq %rax, %xmm0
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120
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96 ; X64-SSE2-NEXT: retq
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77
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97 %bitcast = bitcast i64 %i to <2 x float>
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98 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
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99 ret <2 x float> %fneg
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100 }
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