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annotate test/CodeGen/X86/2008-09-18-inline-asm-2.ll @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
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children 54457678186b
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
95c75e76d11b LLVM 3.4
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2 ; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s
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3 ; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s
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4
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5 ; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
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6 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
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7 ; operand.
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8 ;
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9 ; CHECK: 1st=[[A1:%...]]
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10 ; CHECK-NOT: [[A1]]
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11 ; CHECK: 2nd=[[A2:%...]]
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12 ; CHECK-NOT: [[A1]]
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13 ; CHECK-NOT: [[A2]]
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14 ; CHECK: 3rd=[[A3:%...]]
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15 ; CHECK-NOT: [[A1]]
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16 ; CHECK-NOT: [[A2]]
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17 ; CHECK-NOT: [[A3]]
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18 ; CHECK: 5th=[[A5:%...]]
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19 ; CHECK-NOT: [[A1]]
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20 ; CHECK-NOT: [[A5]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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21 ; CHECK: =4th
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22
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23 ; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th.
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24 ; CHECK: 1%e[[S1:.]]x
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25 ; CHECK: 5%e[[S5:.]]x
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26 ; CHECK-NOT: %[[S1]]
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27 ; CHECK-NOT: %[[S5]]
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28
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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30 target triple = "i386-apple-darwin8"
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31 %struct.foo = type { i32, i32, i8* }
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32
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33 define i32 @get(%struct.foo* %c, i8* %state) nounwind {
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34 entry:
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35 %0 = getelementptr %struct.foo* %c, i32 0, i32 0 ; <i32*> [#uses=2]
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36 %1 = getelementptr %struct.foo* %c, i32 0, i32 1 ; <i32*> [#uses=2]
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37 %2 = getelementptr %struct.foo* %c, i32 0, i32 2 ; <i8**> [#uses=2]
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38 %3 = load i32* %0, align 4 ; <i32> [#uses=1]
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39 %4 = load i32* %1, align 4 ; <i32> [#uses=1]
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40 %5 = load i8* %state, align 1 ; <i8> [#uses=1]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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41 %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3]
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42 %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1]
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43 %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1]
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44 store i32 %asmresult1, i32* %0
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45 %asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2 ; <i32> [#uses=1]
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46 store i32 %asmresult2, i32* %1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 ret i32 %asmresult
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48 }