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annotate test/CodeGen/X86/load-slice.ll @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children 54457678186b
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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1 ; RUN: llc -mtriple x86_64-apple-macosx -mcpu=corei7-avx -combiner-stress-load-slicing < %s -o - | FileCheck %s --check-prefix=STRESS
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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2 ; RUN: llc -mtriple x86_64-apple-macosx -mcpu=corei7-avx < %s -o - | FileCheck %s --check-prefix=REGULAR
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 ; <rdar://problem/14477220>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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6 %class.Complex = type { float, float }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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9 ; Check that independant slices leads to independant loads then the slices leads to
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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10 ; different register file.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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11 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 ; The layout is:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
13 ; LSB 0 1 2 3 | 4 5 6 7 MSB
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
14 ; Low High
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
15 ; The base address points to 0 and is 8-bytes aligned.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
16 ; Low slice starts at 0 (base) and is 8-bytes aligned.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
17 ; High slice starts at 4 (base + 4-bytes) and is 4-bytes aligned.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 ; STRESS-LABEL: t1:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 ; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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21 ; STRESS: vmovss 64([[BASE:[^(]+]]), [[OUT_Real:%xmm[0-9]+]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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22 ; Add low slice: out[out_start].real, this is base + 0.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
23 ; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
24 ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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25 ; STRESS-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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26 ; Add high slice: out[out_start].imm, this is base + 4.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 ; STRESS-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 ; Swap Imm and Real.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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29 ; STRESS-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 ; Put the results back into out[out_start].
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 ; STRESS-NEXT: vmovq [[RES_Vec]], ([[BASE]])
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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32 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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33 ; Same for REGULAR, we eliminate register bank copy with each slices.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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34 ; REGULAR-LABEL: t1:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35 ; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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36 ; REGULAR: vmovss 64([[BASE:[^)]+]]), [[OUT_Real:%xmm[0-9]+]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 ; Add low slice: out[out_start].real, this is base + 0.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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38 ; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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39 ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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40 ; REGULAR-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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41 ; Add high slice: out[out_start].imm, this is base + 4.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 ; REGULAR-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 ; Swap Imm and Real.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 ; REGULAR-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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45 ; Put the results back into out[out_start].
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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46 ; REGULAR-NEXT: vmovq [[RES_Vec]], ([[BASE]])
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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47 define void @t1(%class.Complex* nocapture %out, i64 %out_start) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48 entry:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49 %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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50 %tmp = bitcast %class.Complex* %arrayidx to i64*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 %tmp1 = load i64* %tmp, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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52 %t0.sroa.0.0.extract.trunc = trunc i64 %tmp1 to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53 %tmp2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54 %t0.sroa.2.0.extract.shift = lshr i64 %tmp1, 32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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55 %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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56 %tmp3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57 %add = add i64 %out_start, 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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58 %arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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59 %i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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60 %tmp4 = load float* %i.i, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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61 %add.i = fadd float %tmp4, %tmp2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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62 %retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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63 %r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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64 %tmp5 = load float* %r.i, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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65 %add5.i = fadd float %tmp5, %tmp3
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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66 %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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67 %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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68 store <2 x float> %retval.sroa.0.4.vec.insert.i, <2 x float>* %ref.tmp.sroa.0.0.cast, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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69 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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70 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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71
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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72 ; Function Attrs: nounwind
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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73 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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74
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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75 ; Function Attrs: nounwind
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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76 declare void @llvm.lifetime.start(i64, i8* nocapture)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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77
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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78 ; Function Attrs: nounwind
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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79 declare void @llvm.lifetime.end(i64, i8* nocapture)
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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80
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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81 ; Check that we do not read outside of the chunk of bits of the original loads.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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82 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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83 ; The 64-bits should have been split in one 32-bits and one 16-bits slices.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
84 ; The 16-bits should be zero extended to match the final type.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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85 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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86 ; The memory layout is:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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87 ; LSB 0 1 2 3 | 4 5 | 6 7 MSB
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
88 ; Low High
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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89 ; The base address points to 0 and is 8-bytes aligned.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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90 ; Low slice starts at 0 (base) and is 8-bytes aligned.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
91 ; High slice starts at 6 (base + 6-bytes) and is 2-bytes aligned.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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92 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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93 ; STRESS-LABEL: t2:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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94 ; STRESS: movzwl 6([[BASE:[^)]+]]), %eax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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95 ; STRESS-NEXT: addl ([[BASE]]), %eax
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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96 ; STRESS-NEXT: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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97 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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98 ; For the REGULAR heuristic, this is not profitable to slice things that are not
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
99 ; next to each other in memory. Here we have a hole with bytes #4-5.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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100 ; REGULAR-LABEL: t2:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
101 ; REGULAR: shrq $48
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
102 define i32 @t2(%class.Complex* nocapture %out, i64 %out_start) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
103 %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
104 %bitcast = bitcast %class.Complex* %arrayidx to i64*
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
105 %chunk64 = load i64* %bitcast, align 8
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
106 %slice32_low = trunc i64 %chunk64 to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
107 %shift48 = lshr i64 %chunk64, 48
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
108 %slice32_high = trunc i64 %shift48 to i32
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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109 %res = add i32 %slice32_high, %slice32_low
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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110 ret i32 %res
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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111 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
112
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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113 ; Check that we do not optimize overlapping slices.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114 ;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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115 ; The 64-bits should NOT have been split in as slices are overlapping.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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116 ; First slice uses bytes numbered 0 to 3.
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117 ; Second slice uses bytes numbered 6 and 7.
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118 ; Third slice uses bytes numbered 4 to 7.
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119 ;
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120 ; STRESS-LABEL: t3:
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121 ; STRESS: shrq $48
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122 ; STRESS: shrq $32
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123 ;
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124 ; REGULAR-LABEL: t3:
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125 ; REGULAR: shrq $48
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126 ; REGULAR: shrq $32
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127 define i32 @t3(%class.Complex* nocapture %out, i64 %out_start) {
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128 %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
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129 %bitcast = bitcast %class.Complex* %arrayidx to i64*
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130 %chunk64 = load i64* %bitcast, align 8
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131 %slice32_low = trunc i64 %chunk64 to i32
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132 %shift48 = lshr i64 %chunk64, 48
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133 %slice32_high = trunc i64 %shift48 to i32
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134 %shift32 = lshr i64 %chunk64, 32
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135 %slice32_lowhigh = trunc i64 %shift32 to i32
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136 %tmpres = add i32 %slice32_high, %slice32_low
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137 %res = add i32 %slice32_lowhigh, %tmpres
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138 ret i32 %res
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139 }