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annotate lib/Target/Mips/Mips.td @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 60c9769439b8
children 7d135dc70f03
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1 //===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 // This is the top level entry point for the Mips target.
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10 //===----------------------------------------------------------------------===//
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11
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12 //===----------------------------------------------------------------------===//
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13 // Target-independent interfaces
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14 //===----------------------------------------------------------------------===//
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15
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16 include "llvm/Target/Target.td"
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17
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18 // The overall idea of the PredicateControl class is to chop the Predicates list
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19 // into subsets that are usually overridden independently. This allows
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20 // subclasses to partially override the predicates of their superclasses without
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21 // having to re-add all the existing predicates.
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22 class PredicateControl {
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23 // Predicates for the encoding scheme in use such as HasStdEnc
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24 list<Predicate> EncodingPredicates = [];
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25 // Predicates for the GPR size such as IsGP64bit
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26 list<Predicate> GPRPredicates = [];
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27 // Predicates for the FGR size and layout such as IsFP64bit
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28 list<Predicate> FGRPredicates = [];
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29 // Predicates for the instruction group membership such as ISA's and ASE's
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30 list<Predicate> InsnPredicates = [];
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31 // Predicate for marking the instruction as usable in hard-float mode only.
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32 list<Predicate> HardFloatPredicate = [];
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33 // Predicates for anything else
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34 list<Predicate> AdditionalPredicates = [];
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35 list<Predicate> Predicates = !listconcat(EncodingPredicates,
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36 GPRPredicates,
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37 FGRPredicates,
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38 InsnPredicates,
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39 HardFloatPredicate,
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40 AdditionalPredicates);
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41 }
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42
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43 // Like Requires<> but for the AdditionalPredicates list
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44 class AdditionalRequires<list<Predicate> preds> {
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45 list<Predicate> AdditionalPredicates = preds;
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46 }
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47
0
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48 //===----------------------------------------------------------------------===//
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49 // Register File, Calling Conv, Instruction Descriptions
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50 //===----------------------------------------------------------------------===//
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51
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52 include "MipsRegisterInfo.td"
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53 include "MipsSchedule.td"
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54 include "MipsInstrInfo.td"
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55 include "MipsCallingConv.td"
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56
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57 def MipsInstrInfo : InstrInfo;
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58
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59 //===----------------------------------------------------------------------===//
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60 // Mips Subtarget features //
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61 //===----------------------------------------------------------------------===//
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62
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63 def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true",
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64 "Disable SVR4-style position-independent code">;
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65 def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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66 "General Purpose Registers are 64-bit wide">;
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67 def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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68 "Support 64-bit FP registers">;
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69 def FeatureFPXX : SubtargetFeature<"fpxx", "IsFPXX", "true",
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70 "Support for FPXX">;
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71 def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
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72 "IEEE 754-2008 NaN encoding">;
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73 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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74 "true", "Only supports single precision float">;
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75 def FeatureSoftFloat : SubtargetFeature<"soft-float", "IsSoftFloat", "true",
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76 "Does not support floating point instructions">;
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77 def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
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78 "Disable odd numbered single-precision "
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79 "registers">;
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80 def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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81 "true", "Enable vector FPU instructions">;
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82 def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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83 "Mips I ISA Support [highly experimental]">;
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84 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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85 "Mips II ISA Support [highly experimental]",
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86 [FeatureMips1]>;
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87 def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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88 "Subset of MIPS-III that is also in MIPS32 "
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89 "[highly experimental]">;
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90 def FeatureMips3_32r2 : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
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91 "Subset of MIPS-III that is also in MIPS32r2 "
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92 "[highly experimental]">;
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93 def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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94 "MIPS III ISA Support [highly experimental]",
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95 [FeatureMips2, FeatureMips3_32,
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96 FeatureMips3_32r2, FeatureGP64Bit,
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97 FeatureFP64Bit]>;
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98 def FeatureMips4_32 : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
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99 "Subset of MIPS-IV that is also in MIPS32 "
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100 "[highly experimental]">;
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101 def FeatureMips4_32r2 : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
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102 "Subset of MIPS-IV that is also in MIPS32r2 "
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103 "[highly experimental]">;
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104 def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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105 "Mips4", "MIPS IV ISA Support",
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106 [FeatureMips3, FeatureMips4_32,
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107 FeatureMips4_32r2]>;
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108 def FeatureMips5_32r2 : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
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109 "Subset of MIPS-V that is also in MIPS32r2 "
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110 "[highly experimental]">;
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111 def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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112 "MIPS V ISA Support [highly experimental]",
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113 [FeatureMips4, FeatureMips5_32r2]>;
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114 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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115 "Mips32 ISA Support",
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116 [FeatureMips2, FeatureMips3_32,
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117 FeatureMips4_32]>;
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118 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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119 "Mips32r2", "Mips32r2 ISA Support",
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120 [FeatureMips3_32r2, FeatureMips4_32r2,
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121 FeatureMips5_32r2, FeatureMips32]>;
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122 def FeatureMips32r3 : SubtargetFeature<"mips32r3", "MipsArchVersion",
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123 "Mips32r3", "Mips32r3 ISA Support",
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diff changeset
124 [FeatureMips32r2]>;
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parents: 83
diff changeset
125 def FeatureMips32r5 : SubtargetFeature<"mips32r5", "MipsArchVersion",
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parents: 83
diff changeset
126 "Mips32r5", "Mips32r5 ISA Support",
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parents: 83
diff changeset
127 [FeatureMips32r3]>;
77
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parents: 33
diff changeset
128 def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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parents: 33
diff changeset
129 "Mips32r6",
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parents: 33
diff changeset
130 "Mips32r6 ISA Support [experimental]",
95
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parents: 83
diff changeset
131 [FeatureMips32r5, FeatureFP64Bit,
77
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parents: 33
diff changeset
132 FeatureNaN2008]>;
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
95c75e76d11b LLVM 3.4
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parents:
diff changeset
134 "Mips64", "Mips64 ISA Support",
77
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parents: 33
diff changeset
135 [FeatureMips5, FeatureMips32]>;
0
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parents:
diff changeset
136 def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 "Mips64r2", "Mips64r2 ISA Support",
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 [FeatureMips64, FeatureMips32r2]>;
95
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parents: 83
diff changeset
139 def FeatureMips64r3 : SubtargetFeature<"mips64r3", "MipsArchVersion",
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parents: 83
diff changeset
140 "Mips64r3", "Mips64r3 ISA Support",
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parents: 83
diff changeset
141 [FeatureMips64r2, FeatureMips32r3]>;
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parents: 83
diff changeset
142 def FeatureMips64r5 : SubtargetFeature<"mips64r5", "MipsArchVersion",
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parents: 83
diff changeset
143 "Mips64r5", "Mips64r5 ISA Support",
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parents: 83
diff changeset
144 [FeatureMips64r3, FeatureMips32r5]>;
77
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parents: 33
diff changeset
145 def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion",
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parents: 33
diff changeset
146 "Mips64r6",
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parents: 33
diff changeset
147 "Mips64r6 ISA Support [experimental]",
95
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parents: 83
diff changeset
148 [FeatureMips32r6, FeatureMips64r5,
77
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parents: 33
diff changeset
149 FeatureNaN2008]>;
0
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parents:
diff changeset
150
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diff changeset
151 def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
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parents:
diff changeset
152 "Mips16 mode">;
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diff changeset
153
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diff changeset
154 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
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parents:
diff changeset
155 def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
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parents:
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156 "Mips DSP-R2 ASE", [FeatureDSP]>;
95
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parents: 83
diff changeset
157 def FeatureDSPR3
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158 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE",
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parents: 83
diff changeset
159 [ FeatureDSP, FeatureDSPR2 ]>;
0
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parents:
diff changeset
160
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161 def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
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parents:
diff changeset
162
95
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163 def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">;
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164
0
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165 def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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parents:
diff changeset
166 "microMips mode">;
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diff changeset
167
77
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diff changeset
168 def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
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diff changeset
169 "true", "Octeon cnMIPS Support",
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parents: 33
diff changeset
170 [FeatureMips64r2]>;
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parents: 33
diff changeset
171
95
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diff changeset
172 def FeatureUseTCCInDIV : SubtargetFeature<
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173 "use-tcc-in-div",
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parents: 83
diff changeset
174 "UseTCCInDIV", "false",
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parents: 83
diff changeset
175 "Force the assembler to use trapping">;
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176
0
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diff changeset
177 //===----------------------------------------------------------------------===//
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178 // Mips processors supported.
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179 //===----------------------------------------------------------------------===//
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180
95
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181 def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
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182 "MipsSubtarget::CPU::P5600",
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parents: 83
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183 "The P5600 Processor", [FeatureMips32r5]>;
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184
0
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185 class Proc<string Name, list<SubtargetFeature> Features>
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parents:
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186 : Processor<Name, MipsGenericItineraries, Features>;
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parents:
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187
83
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188 def : Proc<"mips1", [FeatureMips1]>;
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189 def : Proc<"mips2", [FeatureMips2]>;
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parents: 77
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190 def : Proc<"mips32", [FeatureMips32]>;
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parents: 77
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191 def : Proc<"mips32r2", [FeatureMips32r2]>;
95
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192 def : Proc<"mips32r3", [FeatureMips32r3]>;
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193 def : Proc<"mips32r5", [FeatureMips32r5]>;
83
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parents: 77
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194 def : Proc<"mips32r6", [FeatureMips32r6]>;
77
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diff changeset
195
83
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196 def : Proc<"mips3", [FeatureMips3]>;
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197 def : Proc<"mips4", [FeatureMips4]>;
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198 def : Proc<"mips5", [FeatureMips5]>;
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199 def : Proc<"mips64", [FeatureMips64]>;
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parents: 77
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200 def : Proc<"mips64r2", [FeatureMips64r2]>;
95
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diff changeset
201 def : Proc<"mips64r3", [FeatureMips64r3]>;
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parents: 83
diff changeset
202 def : Proc<"mips64r5", [FeatureMips64r5]>;
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
203 def : Proc<"mips64r6", [FeatureMips64r6]>;
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parents: 77
diff changeset
204 def : Proc<"mips16", [FeatureMips16]>;
60c9769439b8 LLVM 3.7
Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
diff changeset
205 def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
95
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parents: 83
diff changeset
206 def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
0
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parents:
diff changeset
207
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diff changeset
208 def MipsAsmParser : AsmParser {
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parents:
diff changeset
209 let ShouldEmitMatchRegisterName = 0;
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parents:
diff changeset
210 let MnemonicContainsDot = 1;
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parents:
diff changeset
211 }
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parents:
diff changeset
212
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parents:
diff changeset
213 def MipsAsmParserVariant : AsmParserVariant {
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parents:
diff changeset
214 int Variant = 0;
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parents:
diff changeset
215
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parents:
diff changeset
216 // Recognize hard coded registers.
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parents:
diff changeset
217 string RegisterPrefix = "$";
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parents:
diff changeset
218 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
219
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parents:
diff changeset
220 def Mips : Target {
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diff changeset
221 let InstructionSet = MipsInstrInfo;
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parents:
diff changeset
222 let AssemblyParsers = [MipsAsmParser];
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parents:
diff changeset
223 let AssemblyParserVariants = [MipsAsmParserVariant];
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parents:
diff changeset
224 }