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annotate test/CodeGen/ARM/avoid-cpsr-rmw.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 95c75e76d11b
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95
afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-CORTEX
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parents: 0
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2 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=swift | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SWIFT
0
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parents:
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3 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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4 ; dependency) when it isn't dependent on last CPSR defining instruction.
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parents:
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5 ; rdar://8928208
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6
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parents:
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7 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
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8 entry:
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9 ; CHECK-LABEL: t1:
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afa8332a0e37 LLVM 3.8
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parents: 0
diff changeset
10 ; CHECK-CORTEX: muls [[REG:(r[0-9]+)]], r3, r2
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parents: 0
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11 ; CHECK-CORTEX-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
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parents: 0
diff changeset
12 ; CHECK-SWIFT: muls [[REG2:(r[0-9]+)]], r1, r0
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parents: 0
diff changeset
13 ; CHECK-SWIFT-NEXT: mul [[REG:(r[0-9]+)]], r2, r3
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
14 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
15 %0 = mul nsw i32 %a, %b
95c75e76d11b LLVM 3.4
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parents:
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16 %1 = mul nsw i32 %c, %d
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parents:
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17 %2 = mul nsw i32 %0, %1
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parents:
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18 ret i32 %2
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parents:
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19 }
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parents:
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20
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21 ; Avoid partial CPSR dependency via loop backedge.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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22 ; rdar://10357570
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parents:
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23 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
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parents:
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24 entry:
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parents:
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25 ; CHECK-LABEL: t2:
95
afa8332a0e37 LLVM 3.8
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parents: 0
diff changeset
26 br label %while.body
0
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27
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28 while.body:
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29 ; CHECK: while.body
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parents:
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30 ; CHECK: mul r{{[0-9]+}}
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parents:
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31 ; CHECK-NOT: muls
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32 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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parents:
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33 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
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parents: 0
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34 %0 = load i32, i32* %ptr1.addr.09, align 4
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parents: 0
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35 %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
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36 %1 = load i32, i32* %arrayidx1, align 4
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parents: 0
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37 %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
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parents: 0
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38 %2 = load i32, i32* %arrayidx3, align 4
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parents: 0
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39 %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
afa8332a0e37 LLVM 3.8
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parents: 0
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40 %3 = load i32, i32* %arrayidx4, align 4
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parents: 0
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41 %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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42 %mul = mul i32 %1, %0
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parents:
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43 %mul5 = mul i32 %mul, %2
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parents:
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44 %mul6 = mul i32 %mul5, %3
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parents:
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45 store i32 %mul6, i32* %ptr2.addr.08, align 4
95
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parents: 0
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46 %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
0
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parents:
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47 %tobool = icmp eq i32* %incdec.ptr, null
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parents:
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48 br i1 %tobool, label %while.end, label %while.body
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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49
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50 while.end:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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51 ret void
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parents:
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52 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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53
95c75e76d11b LLVM 3.4
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54 ; Allow partial CPSR dependency when code size is the priority.
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parents:
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55 ; rdar://12878928
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parents:
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56 define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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57 entry:
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58 ; CHECK-LABEL: t3:
95
afa8332a0e37 LLVM 3.8
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59 br label %while.body
0
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60
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61 while.body:
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62 ; CHECK: while.body
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parents:
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63 ; CHECK: mul r{{[0-9]+}}
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parents:
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64 ; CHECK: muls
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parents:
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65 %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
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parents:
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66 %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
95
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parents: 0
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67 %0 = load i32, i32* %ptr1.addr.09, align 4
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parents: 0
diff changeset
68 %arrayidx1 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 1
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parents: 0
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69 %1 = load i32, i32* %arrayidx1, align 4
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parents: 0
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70 %arrayidx3 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 2
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parents: 0
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71 %2 = load i32, i32* %arrayidx3, align 4
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parents: 0
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72 %arrayidx4 = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 3
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parents: 0
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73 %3 = load i32, i32* %arrayidx4, align 4
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parents: 0
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74 %add.ptr = getelementptr inbounds i32, i32* %ptr1.addr.09, i32 4
0
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parents:
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75 %mul = mul i32 %1, %0
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parents:
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76 %mul5 = mul i32 %mul, %2
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parents:
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77 %mul6 = mul i32 %mul5, %3
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parents:
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78 store i32 %mul6, i32* %ptr2.addr.08, align 4
95
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parents: 0
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79 %incdec.ptr = getelementptr inbounds i32, i32* %ptr2.addr.08, i32 -1
0
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parents:
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80 %tobool = icmp eq i32* %incdec.ptr, null
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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81 br i1 %tobool, label %while.end, label %while.body
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82
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83 while.end:
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84 ret void
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parents:
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85 }
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parents:
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86
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87 ; Avoid producing tMOVi8 after a high-latency flag-setting operation.
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parents:
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88 ; <rdar://problem/13468102>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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89 define void @t4(i32* nocapture %p, double* nocapture %q) {
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parents:
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90 entry:
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parents:
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91 ; CHECK: t4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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92 ; CHECK: vmrs APSR_nzcv, fpscr
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
93 ; CHECK: if.then
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parents:
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94 ; CHECK-NOT: movs
95
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parents: 0
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95 %0 = load double, double* %q, align 4
0
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parents:
diff changeset
96 %cmp = fcmp olt double %0, 1.000000e+01
95
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parents: 0
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97 %incdec.ptr1 = getelementptr inbounds i32, i32* %p, i32 1
0
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parents:
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98 br i1 %cmp, label %if.then, label %if.else
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parents:
diff changeset
99
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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100 if.then:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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101 store i32 7, i32* %p, align 4
95
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parents: 0
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102 %incdec.ptr2 = getelementptr inbounds i32, i32* %p, i32 2
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
103 store i32 8, i32* %incdec.ptr1, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
104 store i32 9, i32* %incdec.ptr2, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
105 br label %if.end
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
106
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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107 if.else:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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108 store i32 3, i32* %p, align 4
95
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parents: 0
diff changeset
109 %incdec.ptr5 = getelementptr inbounds i32, i32* %p, i32 2
0
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parents:
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110 store i32 5, i32* %incdec.ptr1, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
111 store i32 6, i32* %incdec.ptr5, align 4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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112 br label %if.end
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
113
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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114 if.end:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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115 ret void
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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116 }