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annotate test/CodeGen/X86/i486-fence-loop.ll @ 95:afa8332a0e37 LLVM3.8

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LLVM 3.8
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Tue, 13 Oct 2015 17:48:58 +0900
parents 95c75e76d11b
children 803732b1fca8
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95c75e76d11b LLVM 3.4
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1 ; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s
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3 ; Main test here was that ISelDAG could cope with a MachineNode in the chain
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4 ; from the first load to the "X86ISD::SUB". Previously it thought that meant no
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5 ; cycle could be formed so it tried to use "sub (%eax), [[RHS]]".
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7 define void @gst_atomic_queue_push(i32* %addr) {
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8 ; CHECK-LABEL: gst_atomic_queue_push:
95c75e76d11b LLVM 3.4
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9 ; CHECK: movl (%eax), [[LHS:%e[a-z]+]]
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10 ; CHECK: lock orl
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11 ; CHECK: movl (%eax), [[RHS:%e[a-z]+]]
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12 ; CHECK: cmpl [[LHS]], [[RHS]]
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14 entry:
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15 br label %while.body
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17 while.body:
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18 %0 = load volatile i32, i32* %addr, align 4
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19 fence seq_cst
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20 %1 = load volatile i32, i32* %addr, align 4
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21 %cmp = icmp sgt i32 %1, %0
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22 br i1 %cmp, label %while.body, label %if.then
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23
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24 if.then:
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25 ret void
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26 }