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1 //===--- HexagonPseudo.td -------------------------------------------------===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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121
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6 //
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7 //===----------------------------------------------------------------------===//
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8
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9 // The pat frags in the definitions below need to have a named register,
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10 // otherwise i32 will be assumed regardless of the register class. The
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11 // name of the register does not matter.
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12 def I1 : PatLeaf<(i1 PredRegs:$R)>;
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13 def I32 : PatLeaf<(i32 IntRegs:$R)>;
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14 def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
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15 def F32 : PatLeaf<(f32 IntRegs:$R)>;
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16 def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
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17
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18 let PrintMethod = "printGlobalOperand" in {
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19 def globaladdress : Operand<i32>;
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20 def globaladdressExt : Operand<i32>;
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21 }
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22
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23 let isPseudo = 1 in {
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24 let isCodeGenOnly = 0 in
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25 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
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26 (ins s27_2Imm:$Ii), "${Rd32} = iconst(#${Ii})">;
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27
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28 def DUPLEX_Pseudo : InstHexagon<(outs),
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29 (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>;
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30 }
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31
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32 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
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33 isAsmParserOnly = 1 in
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34 def TFRI64_V2_ext : InstHexagon<(outs DoubleRegs:$dst),
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35 (ins s32_0Imm:$src1, s8_0Imm:$src2),
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36 "$dst = combine(#$src1,#$src2)", [], "",
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37 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
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38
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39 // HI/LO Instructions
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40 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
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41 hasNewValue = 1, opNewValue = 0 in
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42 class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
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43 InstHexagon rootInst>
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44 : InstHexagon<(outs IntRegs:$dst),
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45 (ins u16_0Imm:$imm_value),
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46 "$dst"#RegHalf#" = #$imm_value", [], "",
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47 rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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48 bits<5> dst;
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49 bits<32> imm_value;
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50
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51 let Inst{27} = Rs;
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52 let Inst{26-24} = MajOp;
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53 let Inst{21} = MinOp;
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54 let Inst{20-16} = dst;
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55 let Inst{23-22} = imm_value{15-14};
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56 let Inst{13-0} = imm_value{13-0};
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57 }
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58
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59 let isAsmParserOnly = 1 in {
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60 def LO : REG_IMMED<".l", 0b0, 0b001, 0b1, A2_tfril>;
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61 def HI : REG_IMMED<".h", 0b0, 0b010, 0b1, A2_tfrih>;
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62 }
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63
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64 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
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65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
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66 "$Rd = CONST32(#$v)", []>;
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67 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
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68 "$Rd = CONST64(#$v)", []>;
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69 }
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70
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71 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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72 isCodeGenOnly = 1 in
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73 def PS_true : InstHexagon<(outs PredRegs:$dst), (ins), "",
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74 [(set I1:$dst, 1)], "", C2_orn.Itinerary, TypeCR>;
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75
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76 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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77 isCodeGenOnly = 1 in
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78 def PS_false : InstHexagon<(outs PredRegs:$dst), (ins), "",
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79 [(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
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80
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81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
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82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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83 ".error \"should not emit\" ", []>;
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84
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85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
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86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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87 ".error \"should not emit\" ", []>;
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88
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89
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90 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
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92 def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset),
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93 ":endloop0",
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94 []>;
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95 }
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96
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97 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
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99 def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset),
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100 ":endloop1",
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101 []>;
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102 }
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103
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104 let isBranch = 1, isTerminator = 1, hasSideEffects = 0,
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105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
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106 def ENDLOOP01 : Endloop<(outs), (ins b30_2Imm:$offset),
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107 ":endloop01",
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108 []>;
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109 }
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110
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111 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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112 opExtendable = 0, hasSideEffects = 0 in
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113 class LOOP_iBase<string mnemonic, InstHexagon rootInst>
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114 : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2),
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115 #mnemonic#"($offset,#$src2)",
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116 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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117 bits<9> offset;
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118 bits<10> src2;
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119
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120 let IClass = 0b0110;
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121
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122 let Inst{27-22} = 0b100100;
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123 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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124 let Inst{20-16} = src2{9-5};
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125 let Inst{12-8} = offset{8-4};
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126 let Inst{7-5} = src2{4-2};
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127 let Inst{4-3} = offset{3-2};
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128 let Inst{1-0} = src2{1-0};
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129 }
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130
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131 let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
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132 opExtendable = 0, hasSideEffects = 0 in
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133 class LOOP_rBase<string mnemonic, InstHexagon rootInst>
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134 : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
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135 #mnemonic#"($offset,$src2)",
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136 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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137 bits<9> offset;
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138 bits<5> src2;
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139
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140 let IClass = 0b0110;
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141
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142 let Inst{27-22} = 0b000000;
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143 let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1);
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144 let Inst{20-16} = src2;
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145 let Inst{12-8} = offset{8-4};
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146 let Inst{4-3} = offset{3-2};
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147 }
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148
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149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
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150 opExtendable = 0 in {
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151 def J2_loop0iext : LOOP_iBase<"loop0", J2_loop0i>;
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152 def J2_loop1iext : LOOP_iBase<"loop1", J2_loop1i>;
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153 }
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154
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155 // Interestingly only loop0's appear to set usr.lpcfg
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156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
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157 def J2_loop0rext : LOOP_rBase<"loop0", J2_loop0r>;
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158 def J2_loop1rext : LOOP_rBase<"loop1", J2_loop1r>;
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159 }
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160
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161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
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162 isExtended = 0, isExtendable = 1, opExtendable = 0,
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163 isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
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164 class T_Call<string ExtStr>
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165 : InstHexagon<(outs), (ins a30_2Imm:$dst),
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166 "call " # ExtStr # "$dst", [], "", J2_call.Itinerary, TypeJ>,
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167 OpcodeHexagon {
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168 let BaseOpcode = "call";
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169 bits<24> dst;
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170
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171 let IClass = 0b0101;
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172 let Inst{27-25} = 0b101;
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173 let Inst{24-16,13-1} = dst{23-2};
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174 let Inst{0} = 0b0;
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175 }
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176
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177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
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178 isPredicable = 0 in
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179 def CALLProfile : T_Call<"">;
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180
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181 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1,
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182 Defs = [PC, R31, R6, R7, P0] in
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183 def PS_call_stk : T_Call<"">;
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184
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185 // Call, no return.
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186 let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
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187 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
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188 "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
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189 bits<5> Rs;
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190 bits<2> Pu;
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191 let isPredicatedFalse = 1;
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192
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193 let IClass = 0b0101;
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194 let Inst{27-21} = 0b0000101;
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195 let Inst{20-16} = Rs;
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196 }
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197
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198 let isCall = 1, hasSideEffects = 1,
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199 isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
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200 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
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201 class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops,
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202 InstrItinClass itin>
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203 : Pseudo<(outs), iops, "">, PredRel {
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204 bits<2> Pu;
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205 bits<17> dst;
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206 let opExtentBits = nbits;
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207 let isPredicable = 0; // !if(isPred, 0, 1);
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208 let isPredicated = 0; // isPred;
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209 let isPredicatedFalse = isFalse;
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210 let Itinerary = itin;
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121
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211 }
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212
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213 def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii), J2_call.Itinerary>;
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214 //def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst),
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215 // J2_callt.Itinerary>;
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216 //def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst),
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217 // J2_callf.Itinerary>;
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218
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219 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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220 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
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221 cofMax1 = 1 in
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222 class T_JMPr <InstHexagon rootInst>
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223 : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
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224 "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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225 bits<5> dst;
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226
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227 let IClass = 0b0101;
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228 let Inst{27-21} = 0b0010100;
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229 let Inst{20-16} = dst;
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230 }
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231
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232 // A return through builtin_eh_return.
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233 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
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234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
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235 def EH_RETURN_JMPR : T_JMPr<J2_jumpr>;
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236
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237 // Indirect tail-call.
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238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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239 isTerminator = 1, isCodeGenOnly = 1 in
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240 def PS_tailcall_r : T_JMPr<J2_jumpr>;
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241
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242 //
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243 // Direct tail-calls.
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244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
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245 isTerminator = 1, isCodeGenOnly = 1 in
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246 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
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247
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248 let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
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249 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
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250
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251 // Generate frameindex addresses. The main reason for the offset operand is
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252 // that every instruction that is allowed to have frame index as an operand
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253 // will then have that operand followed by an immediate operand (the offset).
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254 // This simplifies the frame-index elimination code.
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255 //
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256 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
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257 isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0, isExtendable = 1,
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258 isExtentSigned = 1, opExtentBits = 16, opExtentAlign = 0 in {
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259 let opExtendable = 2 in
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260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
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261 (ins IntRegs:$fi, s32_0Imm:$off), "">;
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262 let opExtendable = 3 in
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263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
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264 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
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265 }
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266
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267 class CondStr<string CReg, bit True, bit New> {
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268 string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
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269 }
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270 class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
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271 string S = Mnemonic # !if(Taken, ":t", ":nt");
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272 }
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273 let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
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274 hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
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275 class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak, InstHexagon rootInst>
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276 : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
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277 CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
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278 JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
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279 [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
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280
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281 let isTaken = isTak;
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282 let isPredicatedFalse = PredNot;
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283 let isPredicatedNew = isPredNew;
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284 bits<2> src;
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285 bits<5> dst;
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286
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287 let IClass = 0b0101;
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288
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289 let Inst{27-22} = 0b001101;
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290 let Inst{21} = PredNot;
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291 let Inst{20-16} = dst;
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292 let Inst{12} = isTak;
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293 let Inst{11} = isPredNew;
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294 let Inst{9-8} = src;
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295 }
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296
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297 let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
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298 isBarrier = 1, BaseOpcode = "JMPret" in {
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299 def PS_jmpret : T_JMPr<J2_jumpr>, PredNewRel;
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300 def PS_jmprett : T_JMPr_c<0, 0, 0, J2_jumprt>, PredNewRel;
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301 def PS_jmpretf : T_JMPr_c<1, 0, 0, J2_jumprf>, PredNewRel;
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302 def PS_jmprettnew : T_JMPr_c<0, 1, 0, J2_jumprtnew>, PredNewRel;
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303 def PS_jmpretfnew : T_JMPr_c<1, 1, 0, J2_jumprfnew>, PredNewRel;
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304 def PS_jmprettnewpt : T_JMPr_c<0, 1, 1, J2_jumprtnewpt>, PredNewRel;
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305 def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel;
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306 }
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307
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308 //defm V6_vtran2x2_map : HexagonMapping<(outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, HvxVR:$Vx32in, IntRegs:$Rt32)>;
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309
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310 // The reason for the custom inserter is to record all ALLOCA instructions
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311 // in MachineFunctionInfo.
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312 let Defs = [R29], hasSideEffects = 1 in
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313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
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314 (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
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315
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316 // Load predicate.
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317 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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318 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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319 def LDriw_pred : LDInst<(outs PredRegs:$dst),
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320 (ins IntRegs:$addr, s32_0Imm:$off),
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321 ".error \"should not emit\"", []>;
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322
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323 // Load modifier.
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324 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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325 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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147
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326 def LDriw_ctr : LDInst<(outs CtrRegs:$dst),
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121
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327 (ins IntRegs:$addr, s32_0Imm:$off),
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328 ".error \"should not emit\"", []>;
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329
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330
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331 let isCodeGenOnly = 1, isPseudo = 1 in
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332 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
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333 (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
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334 ".error \"should not emit\" ", [], "", A2_tfrpt.Itinerary, TypeALU32_2op>;
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335
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336 let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
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337 isPredicable = 1,
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338 isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
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339 opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
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340 class T_JMP: InstHexagon<(outs), (ins b30_2Imm:$dst),
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341 "jump $dst",
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342 [], "", J2_jump.Itinerary, TypeJ>, OpcodeHexagon {
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343 bits<24> dst;
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344 let IClass = 0b0101;
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345
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346 let Inst{27-25} = 0b100;
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347 let Inst{24-16} = dst{23-15};
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348 let Inst{13-1} = dst{14-2};
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349 }
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350
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351 // Restore registers and dealloc return function call.
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352 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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354 def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP;
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355
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356 let isExtended = 1, opExtendable = 0 in
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357 def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP;
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358
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359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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360 def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP;
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361
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362 let isExtended = 1, opExtendable = 0 in
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363 def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP;
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364 }
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365 }
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366
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367 // Restore registers and dealloc frame before a tail call.
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368 let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
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369 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel;
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370
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371 let isExtended = 1, opExtendable = 0 in
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372 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel;
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373
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374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
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375 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel;
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376
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377 let isExtended = 1, opExtendable = 0 in
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378 def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel;
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379 }
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380 }
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381
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382 // Save registers function call.
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383 let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in {
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384 def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel;
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385
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386 let isExtended = 1, opExtendable = 0 in
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387 def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel;
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388
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389 let Defs = [P0] in
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390 def SAVE_REGISTERS_CALL_V4STK : T_Call<"">, PredRel;
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391
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392 let Defs = [P0], isExtended = 1, opExtendable = 0 in
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393 def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<"">, PredRel;
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394
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395 let Defs = [R14, R15, R28] in
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396 def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel;
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397
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398 let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in
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399 def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel;
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400
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401 let Defs = [R14, R15, R28, P0] in
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402 def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<"">, PredRel;
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403
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404 let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in
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405 def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel;
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406 }
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407
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408 // Vector store pseudos
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147
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409 let Predicates = [HasV60,UseHVX], isPseudo = 1, isCodeGenOnly = 1,
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121
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410 mayStore = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
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411 class STrivv_template<RegisterClass RC, InstHexagon rootInst>
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412 : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src),
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413 "", [], "", rootInst.Itinerary, rootInst.Type>;
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414
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415 def PS_vstorerw_ai: STrivv_template<HvxWR, V6_vS32b_ai>,
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147
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416 Requires<[HasV60,UseHVX]>;
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121
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417 def PS_vstorerw_nt_ai: STrivv_template<HvxWR, V6_vS32b_nt_ai>,
|
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147
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418 Requires<[HasV60,UseHVX]>;
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121
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419 def PS_vstorerwu_ai: STrivv_template<HvxWR, V6_vS32Ub_ai>,
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147
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420 Requires<[HasV60,UseHVX]>;
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121
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421
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422 let isPseudo = 1, isCodeGenOnly = 1, mayStore = 1, hasSideEffects = 0 in
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423 def PS_vstorerq_ai: Pseudo<(outs),
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424 (ins IntRegs:$Rs, s32_0Imm:$Off, HvxQR:$Qt), "", []>,
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147
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425 Requires<[HasV60,UseHVX]>;
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121
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426
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427 // Vector load pseudos
|
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147
|
428 let Predicates = [HasV60, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
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121
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429 mayLoad = 1, accessSize = HVXVectorAccess, hasSideEffects = 0 in
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430 class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
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431 : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
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432 "", [], "", rootInst.Itinerary, rootInst.Type>;
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433
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434 def PS_vloadrw_ai: LDrivv_template<HvxWR, V6_vL32b_ai>,
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147
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435 Requires<[HasV60,UseHVX]>;
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121
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436 def PS_vloadrw_nt_ai: LDrivv_template<HvxWR, V6_vL32b_nt_ai>,
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147
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437 Requires<[HasV60,UseHVX]>;
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121
|
438 def PS_vloadrwu_ai: LDrivv_template<HvxWR, V6_vL32Ub_ai>,
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147
|
439 Requires<[HasV60,UseHVX]>;
|
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121
|
440
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441 let isPseudo = 1, isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in
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442 def PS_vloadrq_ai: Pseudo<(outs HvxQR:$Qd),
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443 (ins IntRegs:$Rs, s32_0Imm:$Off), "", []>,
|
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147
|
444 Requires<[HasV60,UseHVX]>;
|
|
121
|
445
|
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446
|
|
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447 let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
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|
448 class VSELInst<dag outs, dag ins, InstHexagon rootInst>
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|
449 : InstHexagon<outs, ins, "", [], "", rootInst.Itinerary, rootInst.Type>;
|
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450
|
|
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451 def PS_vselect: VSELInst<(outs HvxVR:$dst),
|
|
|
452 (ins PredRegs:$src1, HvxVR:$src2, HvxVR:$src3), V6_vcmov>,
|
|
147
|
453 Requires<[HasV60,UseHVX]>;
|
|
121
|
454 def PS_wselect: VSELInst<(outs HvxWR:$dst),
|
|
|
455 (ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
|
|
147
|
456 Requires<[HasV60,UseHVX]>;
|
|
121
|
457
|
|
134
|
458 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
|
|
|
459 isCodeGenOnly = 1 in {
|
|
|
460 def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
|
|
|
461 V6_veqw.Itinerary, TypeCVI_VA>;
|
|
|
462 def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
|
|
|
463 V6_vgtw.Itinerary, TypeCVI_VA>;
|
|
147
|
464 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
|
|
|
465 V6_vsubw_dv.Itinerary, TypeCVI_VA_DV>;
|
|
134
|
466 }
|
|
|
467
|
|
121
|
468 // Store predicate.
|
|
|
469 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|
|
470 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
|
|
|
471 def STriw_pred : STInst<(outs),
|
|
|
472 (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1),
|
|
|
473 ".error \"should not emit\"", []>;
|
|
|
474 // Store modifier.
|
|
|
475 let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|
|
476 isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
|
|
147
|
477 def STriw_ctr : STInst<(outs),
|
|
|
478 (ins IntRegs:$addr, s32_0Imm:$off, CtrRegs:$src1),
|
|
121
|
479 ".error \"should not emit\"", []>;
|
|
|
480
|
|
|
481 let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
|
|
|
482 isAsmParserOnly = 1 in
|
|
|
483 def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst),
|
|
|
484 (ins u64_0Imm:$src1),
|
|
|
485 "$dst = #$src1", [], "",
|
|
|
486 A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
|
|
|
487
|
|
|
488 // Hexagon doesn't have a vector multiply with C semantics.
|
|
|
489 // Instead, generate a pseudo instruction that gets expaneded into two
|
|
|
490 // scalar MPYI instructions.
|
|
|
491 // This is expanded by ExpandPostRAPseudos.
|
|
|
492 let isPseudo = 1 in
|
|
|
493 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
|
|
|
494 (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>;
|
|
|
495
|
|
|
496 let isPseudo = 1 in
|
|
|
497 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
|
|
|
498 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [],
|
|
|
499 "$Rd = $Rx">;
|
|
|
500
|
|
|
501 def DuplexIClass0: InstDuplex < 0 >;
|
|
|
502 def DuplexIClass1: InstDuplex < 1 >;
|
|
|
503 def DuplexIClass2: InstDuplex < 2 >;
|
|
|
504 let isExtendable = 1 in {
|
|
|
505 def DuplexIClass3: InstDuplex < 3 >;
|
|
|
506 def DuplexIClass4: InstDuplex < 4 >;
|
|
|
507 def DuplexIClass5: InstDuplex < 5 >;
|
|
|
508 def DuplexIClass6: InstDuplex < 6 >;
|
|
|
509 def DuplexIClass7: InstDuplex < 7 >;
|
|
|
510 }
|
|
|
511 def DuplexIClass8: InstDuplex < 8 >;
|
|
|
512 def DuplexIClass9: InstDuplex < 9 >;
|
|
|
513 def DuplexIClassA: InstDuplex < 0xA >;
|
|
|
514 def DuplexIClassB: InstDuplex < 0xB >;
|
|
|
515 def DuplexIClassC: InstDuplex < 0xC >;
|
|
|
516 def DuplexIClassD: InstDuplex < 0xD >;
|
|
|
517 def DuplexIClassE: InstDuplex < 0xE >;
|
|
|
518 def DuplexIClassF: InstDuplex < 0xF >;
|
|
147
|
519
|
|
|
520 // Pseudos for circular buffer instructions. These are needed in order to
|
|
|
521 // allocate the correct pair of CSx and Mx registers.
|
|
|
522 multiclass NewCircularLoad<RegisterClass RC, MemAccessSize MS> {
|
|
|
523
|
|
|
524 let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
|
|
|
525 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
|
|
526 def NAME#_pci : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
|
|
|
527 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs),
|
|
|
528 ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e93a3d71>;
|
|
|
529
|
|
|
530 def NAME#_pcr : LDInst<(outs RC:$Rd32, IntRegs:$Rx32),
|
|
|
531 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs),
|
|
|
532 ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_44d3da28>;
|
|
|
533 }
|
|
|
534 }
|
|
|
535
|
|
|
536 defm PS_loadrub : NewCircularLoad<IntRegs, ByteAccess>;
|
|
|
537 defm PS_loadrb : NewCircularLoad<IntRegs, ByteAccess>;
|
|
|
538 defm PS_loadruh : NewCircularLoad<IntRegs, HalfWordAccess>;
|
|
|
539 defm PS_loadrh : NewCircularLoad<IntRegs, HalfWordAccess>;
|
|
|
540 defm PS_loadri : NewCircularLoad<IntRegs, WordAccess>;
|
|
|
541 defm PS_loadrd : NewCircularLoad<DoubleRegs, DoubleWordAccess>;
|
|
|
542
|
|
|
543 multiclass NewCircularStore<RegisterClass RC, MemAccessSize MS> {
|
|
|
544
|
|
|
545 let isCodeGenOnly = 1, isPseudo = 1, Defs = [CS], Uses = [CS],
|
|
|
546 addrMode = PostInc, accessSize = MS, hasSideEffects = 0 in {
|
|
|
547 def NAME#_pci : STInst<(outs IntRegs:$Rx32),
|
|
|
548 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
|
|
549 ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_e86aa961>;
|
|
|
550
|
|
|
551 def NAME#_pcr : STInst<(outs IntRegs:$Rx32),
|
|
|
552 (ins IntRegs:$Rx32in, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
|
|
|
553 ".error \"should not emit\" ", [], "$Rx32 = $Rx32in", tc_da97ee82>;
|
|
|
554 }
|
|
|
555 }
|
|
|
556
|
|
|
557 defm PS_storerb : NewCircularStore<IntRegs, ByteAccess>;
|
|
|
558 defm PS_storerh : NewCircularStore<IntRegs, HalfWordAccess>;
|
|
|
559 defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>;
|
|
|
560 defm PS_storeri : NewCircularStore<IntRegs, WordAccess>;
|
|
|
561 defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>;
|
|
|
562
|
|
|
563 // A pseudo that generates a runtime crash. This is used to implement
|
|
|
564 // __builtin_trap.
|
|
|
565 let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1, isSolo = 1 in
|
|
|
566 def PS_crash: InstHexagon<(outs), (ins), "", [], "", PSEUDO, TypePSEUDO>;
|
