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annotate lib/Target/Mips/Mips16InstrInfo.h @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 803732b1fca8
children
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1 //===- Mips16InstrInfo.h - Mips16 Instruction Information -------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file contains the Mips16 implementation of the TargetInstrInfo class.
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10 //
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11 //===----------------------------------------------------------------------===//
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13 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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14 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
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16 #include "Mips16RegisterInfo.h"
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17 #include "MipsInstrInfo.h"
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18 #include "llvm/CodeGen/MachineBasicBlock.h"
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19 #include "llvm/Support/MathExtras.h"
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20 #include <cstdint>
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21
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22 namespace llvm {
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23
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24 class MCInstrDesc;
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25 class MipsSubtarget;
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26
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27 class Mips16InstrInfo : public MipsInstrInfo {
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28 const Mips16RegisterInfo RI;
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30 public:
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31 explicit Mips16InstrInfo(const MipsSubtarget &STI);
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33 const MipsRegisterInfo &getRegisterInfo() const override;
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34
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35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
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36 /// load from a stack slot, return the virtual or physical register number of
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37 /// the destination along with the FrameIndex of the loaded stack slot. If
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38 /// not, return 0. This predicate must return 0 if the instruction has
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39 /// any side effects other than loading from the stack slot.
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40 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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41 int &FrameIndex) const override;
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42
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43 /// isStoreToStackSlot - If the specified machine instruction is a direct
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44 /// store to a stack slot, return the virtual or physical register number of
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45 /// the source reg along with the FrameIndex of the loaded stack slot. If
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46 /// not, return 0. This predicate must return 0 if the instruction has
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47 /// any side effects other than storing to the stack slot.
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48 unsigned isStoreToStackSlot(const MachineInstr &MI,
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49 int &FrameIndex) const override;
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50
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51 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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52 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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53 bool KillSrc) const override;
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55 void storeRegToStack(MachineBasicBlock &MBB,
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56 MachineBasicBlock::iterator MBBI,
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57 unsigned SrcReg, bool isKill, int FrameIndex,
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58 const TargetRegisterClass *RC,
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59 const TargetRegisterInfo *TRI,
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60 int64_t Offset) const override;
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62 void loadRegFromStack(MachineBasicBlock &MBB,
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63 MachineBasicBlock::iterator MBBI,
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64 unsigned DestReg, int FrameIndex,
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65 const TargetRegisterClass *RC,
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66 const TargetRegisterInfo *TRI,
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67 int64_t Offset) const override;
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69 bool expandPostRAPseudo(MachineInstr &MI) const override;
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71 unsigned getOppositeBranchOpc(unsigned Opc) const override;
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72
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73 // Adjust SP by FrameSize bytes. Save RA, S0, S1
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74 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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75 MachineBasicBlock::iterator I) const;
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76
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77 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
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78 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
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79 MachineBasicBlock::iterator I) const;
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80
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81 /// Adjust SP by Amount bytes.
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82 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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83 MachineBasicBlock::iterator I) const override;
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84
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85 /// Emit a series of instructions to load an immediate.
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86 // This is to adjust some FrameReg. We return the new register to be used
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87 // in place of FrameReg and the adjusted immediate field (&NewImm)
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88 unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
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89 MachineBasicBlock::iterator II, const DebugLoc &DL,
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90 unsigned &NewImm) const;
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91
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92 static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
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93
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94 static bool validSpImm8(int offset) {
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95 return ((offset & 7) == 0) && isInt<11>(offset);
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96 }
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97
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98 // build the proper one based on the Imm field
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99
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100 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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101
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102 void BuildAddiuSpImm
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103 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
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104
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105 protected:
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106 /// If the specific machine instruction is a instruction that moves/copies
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107 /// value from one register to another register return true along with
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108 /// @Source machine operand and @Destination machine operand.
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109 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
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110 const MachineOperand *&Destination) const override;
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111
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112 private:
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113 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
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114
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115 void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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116 unsigned Opc) const;
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117
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118 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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119 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
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120 MachineBasicBlock::iterator I,
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121 unsigned Reg1, unsigned Reg2) const;
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122
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123 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
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124 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
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125 MachineBasicBlock &MBB,
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126 MachineBasicBlock::iterator I) const;
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127 };
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128
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129 } // end namespace llvm
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131 #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H