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annotate lib/Target/NVPTX/NVPTXPeephole.cpp @ 147:c2174574ed3a

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LLVM 10
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 16:55:33 +0900
parents 3a76565eade5
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===-- NVPTXPeephole.cpp - NVPTX Peephole Optimiztions -------------------===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // In NVPTX, NVPTXFrameLowering will emit following instruction at the beginning
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10 // of a MachineFunction.
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11 //
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12 // mov %SPL, %depot
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13 // cvta.local %SP, %SPL
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14 //
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15 // Because Frame Index is a generic address and alloca can only return generic
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16 // pointer, without this pass the instructions producing alloca'ed address will
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17 // be based on %SP. NVPTXLowerAlloca tends to help replace store and load on
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18 // this address with their .local versions, but this may introduce a lot of
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19 // cvta.to.local instructions. Performance can be improved if we avoid casting
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20 // address back and forth and directly calculate local address based on %SPL.
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21 // This peephole pass optimizes these cases, for example
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22 //
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23 // It will transform the following pattern
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24 // %0 = LEA_ADDRi64 %VRFrame, 4
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25 // %1 = cvta_to_local_yes_64 %0
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26 //
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27 // into
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28 // %1 = LEA_ADDRi64 %VRFrameLocal, 4
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29 //
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30 // %VRFrameLocal is the virtual register name of %SPL
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31 //
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32 //===----------------------------------------------------------------------===//
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33
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34 #include "NVPTX.h"
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35 #include "llvm/CodeGen/MachineFunctionPass.h"
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36 #include "llvm/CodeGen/MachineInstrBuilder.h"
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37 #include "llvm/CodeGen/MachineRegisterInfo.h"
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38 #include "llvm/CodeGen/TargetInstrInfo.h"
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39 #include "llvm/CodeGen/TargetRegisterInfo.h"
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40
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41 using namespace llvm;
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42
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43 #define DEBUG_TYPE "nvptx-peephole"
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44
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45 namespace llvm {
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46 void initializeNVPTXPeepholePass(PassRegistry &);
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47 }
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48
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49 namespace {
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50 struct NVPTXPeephole : public MachineFunctionPass {
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51 public:
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52 static char ID;
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53 NVPTXPeephole() : MachineFunctionPass(ID) {
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54 initializeNVPTXPeepholePass(*PassRegistry::getPassRegistry());
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55 }
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56
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57 bool runOnMachineFunction(MachineFunction &MF) override;
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58
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59 StringRef getPassName() const override {
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60 return "NVPTX optimize redundant cvta.to.local instruction";
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61 }
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62
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63 void getAnalysisUsage(AnalysisUsage &AU) const override {
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64 MachineFunctionPass::getAnalysisUsage(AU);
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65 }
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66 };
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67 }
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68
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69 char NVPTXPeephole::ID = 0;
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70
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71 INITIALIZE_PASS(NVPTXPeephole, "nvptx-peephole", "NVPTX Peephole", false, false)
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72
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73 static bool isCVTAToLocalCombinationCandidate(MachineInstr &Root) {
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74 auto &MBB = *Root.getParent();
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75 auto &MF = *MBB.getParent();
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76 // Check current instruction is cvta.to.local
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77 if (Root.getOpcode() != NVPTX::cvta_to_local_yes_64 &&
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78 Root.getOpcode() != NVPTX::cvta_to_local_yes)
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79 return false;
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80
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81 auto &Op = Root.getOperand(1);
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82 const auto &MRI = MF.getRegInfo();
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83 MachineInstr *GenericAddrDef = nullptr;
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84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
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85 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
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86 }
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87
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88 // Check the register operand is uniquely defined by LEA_ADDRi instruction
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89 if (!GenericAddrDef || GenericAddrDef->getParent() != &MBB ||
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90 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 &&
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91 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) {
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92 return false;
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93 }
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94
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95 // Check the LEA_ADDRi operand is Frame index
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96 auto &BaseAddrOp = GenericAddrDef->getOperand(1);
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97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
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98 return true;
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99 }
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100
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101 return false;
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102 }
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103
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104 static void CombineCVTAToLocal(MachineInstr &Root) {
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105 auto &MBB = *Root.getParent();
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106 auto &MF = *MBB.getParent();
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107 const auto &MRI = MF.getRegInfo();
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108 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
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110
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111 MachineInstrBuilder MIB =
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112 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
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113 Root.getOperand(0).getReg())
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114 .addReg(NVPTX::VRFrameLocal)
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115 .add(Prev.getOperand(2));
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116
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117 MBB.insert((MachineBasicBlock::iterator)&Root, MIB);
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118
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119 // Check if MRI has only one non dbg use, which is Root
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120 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
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121 Prev.eraseFromParentAndMarkDBGValuesForRemoval();
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122 }
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123 Root.eraseFromParentAndMarkDBGValuesForRemoval();
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124 }
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125
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126 bool NVPTXPeephole::runOnMachineFunction(MachineFunction &MF) {
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127 if (skipFunction(MF.getFunction()))
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128 return false;
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129
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130 bool Changed = false;
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131 // Loop over all of the basic blocks.
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132 for (auto &MBB : MF) {
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133 // Traverse the basic block.
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134 auto BlockIter = MBB.begin();
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135
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136 while (BlockIter != MBB.end()) {
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137 auto &MI = *BlockIter++;
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138 if (isCVTAToLocalCombinationCandidate(MI)) {
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139 CombineCVTAToLocal(MI);
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140 Changed = true;
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141 }
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142 } // Instruction
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143 } // Basic Block
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144
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145 // Remove unnecessary %VRFrame = cvta.local %VRFrameLocal
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146 const auto &MRI = MF.getRegInfo();
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147 if (MRI.use_empty(NVPTX::VRFrame)) {
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148 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
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149 MI->eraseFromParentAndMarkDBGValuesForRemoval();
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150 }
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151 }
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152
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153 return Changed;
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154 }
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155
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156 MachineFunctionPass *llvm::createNVPTXPeephole() { return new NVPTXPeephole(); }