Mercurial > hg > CbC > CbC_llvm

comparison lib/Target/Hexagon/HexagonIntrinsics.td @ 134:3a76565eade5 LLVM5.0.1

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update 5.0.1
author mir3636
date Sat, 17 Feb 2018 09:57:20 +0900
parents 803732b1fca8
children c2174574ed3a
comparison
equal deleted inserted replaced
133:c60214abe0e8 134:3a76565eade5
733 733
734 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32) 734 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
735 def : Pat <(int_hexagon_A2_neg I32:$Rs), 735 def : Pat <(int_hexagon_A2_neg I32:$Rs),
736 (A2_subri 0, I32:$Rs)>; 736 (A2_subri 0, I32:$Rs)>;
737 737
738 // Make sure the patterns with zero immediate value has higher complexity
739 // otherwise, we need to updated the predicates for immediates to exclude zero
740 let AddedComplexity = 200 in {
741 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
742 (A2_tfr I32:$Rs)>;
743 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
744 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
745 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
746 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
747 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
748 (S2_vsathub I64:$Rs)>;
749 }
750
751 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm),
752 (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
753 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm),
754 (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
755 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
756 (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
757 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
758 (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
759
738 // Transfer immediate 760 // Transfer immediate
739 def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is), 761 def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is),
740 (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>; 762 (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>;
741 def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is), 763 def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is),
742 (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>; 764 (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>;
1358 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>; 1380 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>;
1359 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>; 1381 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>;
1360 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>; 1382 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
1361 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>; 1383 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
1362 1384
1385 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>;
1386 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>;
1387 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>;
1388 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>;
1389
1363 //******************************************************************* 1390 //*******************************************************************
1364 // SYSTEM 1391 // SYSTEM
1365 //******************************************************************* 1392 //*******************************************************************
1366 1393
1367 def: T_R_pat<Y2_dccleana, int_hexagon_Y2_dccleana>; 1394 def: T_R_pat<Y2_dccleana, int_hexagon_Y2_dccleana>;