--- a/lib/Target/Hexagon/HexagonIntrinsics.td	Fri Feb 16 19:10:49 2018 +0900
+++ b/lib/Target/Hexagon/HexagonIntrinsics.td	Sat Feb 17 09:57:20 2018 +0900
@@ -735,6 +735,28 @@
 def : Pat <(int_hexagon_A2_neg I32:$Rs),
            (A2_subri 0, I32:$Rs)>;
 
+// Make sure the patterns with zero immediate value has higher complexity
+// otherwise, we need to updated the predicates for immediates to exclude zero
+let AddedComplexity = 200 in {
+def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
+           (A2_tfr I32:$Rs)>;
+def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
+           (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
+def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
+           (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
+def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
+           (S2_vsathub I64:$Rs)>;
+}
+
+def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm),
+           (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm),
+           (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
+           (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
+def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
+           (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
+
 // Transfer immediate
 def  : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is),
             (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>;
@@ -1360,6 +1382,11 @@
 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
 
+defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>;
+defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>;
+defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>;
+defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>;
+
 //*******************************************************************
 //           SYSTEM
 //*******************************************************************