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1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 // This is populated based on the following specs:
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10 // Hexagon V2 Architecture
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11 // Application-Level Specification
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12 // 80-V9418-8 Rev. B
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13 // March 4, 2008
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14 //===----------------------------------------------------------------------===//
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15
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83
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16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
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17 : Pat <(IntID imm:$Is),
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18 (MI imm:$Is)>;
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19
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83
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20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
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21 : Pat <(IntID I32:$Rs),
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22 (MI I32:$Rs)>;
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23
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83
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24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
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25 : Pat <(IntID I64:$Rs),
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120
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26 (MI I64:$Rs)>;
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27
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83
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28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
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29 : Pat<(IntID Imm1:$Is, Imm2:$It),
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30 (MI Imm1:$Is, Imm2:$It)>;
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31
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120
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32 class T_RI_pat <InstHexagon MI, Intrinsic IntID,
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33 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
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83
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34 : Pat<(IntID I32:$Rs, ImmPred:$It),
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35 (MI I32:$Rs, ImmPred:$It)>;
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36
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120
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37 class T_IR_pat <InstHexagon MI, Intrinsic IntID,
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38 PatFrag ImmPred = PatLeaf<(i32 imm)>>
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83
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39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
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40 (MI ImmPred:$Is, I32:$Rt)>;
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41
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83
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42 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
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43 : Pat<(IntID I64:$Rs, imm:$It),
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120
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44 (MI I64:$Rs, imm:$It)>;
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45
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83
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46 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
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47 : Pat<(IntID I32:$Rs, I64:$Rt),
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120
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48 (MI I32:$Rs, I64:$Rt)>;
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49
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83
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50 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
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51 : Pat <(IntID I32:$Rs, I32:$Rt),
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52 (MI I32:$Rs, I32:$Rt)>;
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53
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83
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54 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
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55 : Pat <(IntID I64:$Rs, I64:$Rt),
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120
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56 (MI I64:$Rs, I64:$Rt)>;
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57
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58 class T_QQ_pat <InstHexagon MI, Intrinsic IntID>
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59 : Pat <(IntID I32:$Rs, I32:$Rt),
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60 (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>;
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61
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83
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62 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
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120
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63 : Pat <(IntID I32:$Rp, Imm1:$Is, Imm2:$It),
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64 (MI (C2_tfrrp I32:$Rp), Imm1:$Is, Imm2:$It)>;
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65
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66 class T_QRR_pat <InstHexagon MI, Intrinsic IntID>
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67 : Pat <(IntID I32:$Rp, I32:$Rs, I32:$Rt),
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68 (MI (C2_tfrrp I32:$Rp), I32:$Rs, I32:$Rt)>;
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69
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83
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70 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
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120
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71 : Pat <(IntID I32:$Rp, I32:$Rs, ImmPred:$Is),
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72 (MI (C2_tfrrp I32:$Rp), I32:$Rs, ImmPred:$Is)>;
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73
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83
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74 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
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120
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75 : Pat <(IntID I32:$Rp, ImmPred:$Is, I32:$Rs),
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76 (MI (C2_tfrrp I32:$Rp), ImmPred:$Is, I32:$Rs)>;
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77
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78 class T_QPP_pat <InstHexagon MI, Intrinsic IntID>
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79 : Pat <(IntID I32:$Rp, I64:$Rs, I64:$Rt),
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80 (MI (C2_tfrrp I32:$Rp), I64:$Rs, I64:$Rt)>;
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81
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83
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82 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
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83 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
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84 (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
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85
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83
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86 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
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87 : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
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88 (MI I32:$Rs, imm:$It, imm:$Iu)>;
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89
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83
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90 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
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91 : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
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92 (MI imm:$It, I32:$Rs, imm:$Iu)>;
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93
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83
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94 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
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95 : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
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96 (MI imm:$Is, I32:$Rs, I32:$Rt)>;
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97
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98 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
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99 : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
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100 (MI I32:$Rs, imm:$Is, I32:$Rt)>;
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101
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102 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
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103 : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
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104 (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
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105
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83
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106 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
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107 : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
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120
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108 (MI I64:$Rs, I64:$Rt, imm:$Iu)>;
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109
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83
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110 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
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111 : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
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120
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112 (MI I64:$Rs, imm:$It, imm:$Iu)>;
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113
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114 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
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115 : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
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120
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116 (MI I64:$Rs, I64:$Rt, I64:$Ru)>;
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117
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83
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118 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
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119 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
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120
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120 (MI I64:$Rs, I64:$Rt, I32:$Ru)>;
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121
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83
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122 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
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123 : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
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120
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124 (MI I64:$Rs, I32:$Rt, I32:$Ru)>;
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125
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83
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126 class T_PPQ_pat <InstHexagon MI, Intrinsic IntID>
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120
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127 : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Rp),
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128 (MI I64:$Rs, I64:$Rt, (C2_tfrrp I32:$Rp))>;
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129
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130 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
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131 : Pat <(IntID I64:$Rs, I32:$Rt),
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120
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132 (MI I64:$Rs, I32:$Rt)>;
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133
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134 class T_D_pat <InstHexagon MI, Intrinsic IntID>
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135 : Pat<(IntID (F64:$Rs)),
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136 (MI (F64:$Rs))>;
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137
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83
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138 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
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139 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
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140 : Pat<(IntID F64:$Rs, ImmPred:$It),
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141 (MI F64:$Rs, ImmPred:$It)>;
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142
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83
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143 class T_F_pat <InstHexagon MI, Intrinsic IntID>
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144 : Pat<(IntID F32:$Rs),
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145 (MI F32:$Rs)>;
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146
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83
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147 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
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120
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148 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
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83
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149 : Pat<(IntID F32:$Rs, ImmPred:$It),
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150 (MI F32:$Rs, ImmPred:$It)>;
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151
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83
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152 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
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153 : Pat<(IntID F32:$Rs, F32:$Rt),
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154 (MI F32:$Rs, F32:$Rt)>;
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155
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83
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156 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
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157 : Pat<(IntID F64:$Rs, F64:$Rt),
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158 (MI F64:$Rs, F64:$Rt)>;
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159
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83
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160 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
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161 : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
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162 (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
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163
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83
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164 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
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120
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165 : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, I32:$Rp),
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166 (MI F32:$Rs, F32:$Rt, F32:$Ru, (C2_tfrrp I32:$Rp))>;
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167
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168 class T_Q_RI_pat <InstHexagon MI, Intrinsic IntID,
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169 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
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170 : Pat<(IntID I32:$Rs, ImmPred:$It),
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171 (C2_tfrpr (MI I32:$Rs, ImmPred:$It))>;
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172
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173 class T_Q_RR_pat <InstHexagon MI, Intrinsic IntID>
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174 : Pat <(IntID I32:$Rs, I32:$Rt),
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175 (C2_tfrpr (MI I32:$Rs, I32:$Rt))>;
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176
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177 class T_Q_RP_pat <InstHexagon MI, Intrinsic IntID>
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178 : Pat <(IntID I32:$Rs, I64:$Rt),
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179 (C2_tfrpr (MI I32:$Rs, I64:$Rt))>;
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180
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181 class T_Q_PR_pat <InstHexagon MI, Intrinsic IntID>
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182 : Pat <(IntID I64:$Rs, I32:$Rt),
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183 (C2_tfrpr (MI I64:$Rs, I32:$Rt))>;
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184
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185 class T_Q_PI_pat <InstHexagon MI, Intrinsic IntID>
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186 : Pat<(IntID I64:$Rs, imm:$It),
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187 (C2_tfrpr (MI I64:$Rs, imm:$It))>;
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188
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189 class T_Q_PP_pat <InstHexagon MI, Intrinsic IntID>
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190 : Pat <(IntID I64:$Rs, I64:$Rt),
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191 (C2_tfrpr (MI I64:$Rs, I64:$Rt))>;
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192
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193 class T_Q_Q_pat <InstHexagon MI, Intrinsic IntID>
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194 : Pat <(IntID I32:$Rp),
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195 (C2_tfrpr (MI (C2_tfrrp I32:$Rp)))>;
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196
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197 class T_Q_QQ_pat <InstHexagon MI, Intrinsic IntID>
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198 : Pat <(IntID I32:$Rp, I32:$Rq),
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199 (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq)))>;
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200
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201 class T_Q_FF_pat <InstHexagon MI, Intrinsic IntID>
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202 : Pat<(IntID F32:$Rs, F32:$Rt),
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203 (C2_tfrpr (MI F32:$Rs, F32:$Rt))>;
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204
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205 class T_Q_DD_pat <InstHexagon MI, Intrinsic IntID>
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206 : Pat<(IntID F64:$Rs, F64:$Rt),
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207 (C2_tfrpr (MI F64:$Rs, F64:$Rt))>;
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208
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209 class T_Q_FI_pat <InstHexagon MI, Intrinsic IntID>
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210 : Pat<(IntID F32:$Rs, imm:$It),
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211 (C2_tfrpr (MI F32:$Rs, imm:$It))>;
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212
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213 class T_Q_DI_pat <InstHexagon MI, Intrinsic IntID>
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214 : Pat<(IntID F64:$Rs, imm:$It),
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215 (C2_tfrpr (MI F64:$Rs, imm:$It))>;
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216
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217 class T_Q_QQQ_pat <InstHexagon MI, Intrinsic IntID>
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218 : Pat <(IntID I32:$Rp, I32:$Rq, I32:$Rs),
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219 (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq),
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220 (C2_tfrrp I32:$Rs)))>;
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221
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83
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222 //===----------------------------------------------------------------------===//
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223 // MPYS / Multipy signed/unsigned halfwords
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224 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
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225 //===----------------------------------------------------------------------===//
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226
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83
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227 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
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228 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
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229 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
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230 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
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231 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
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232 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
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233 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
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234 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
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235
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83
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236 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
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237 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
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238 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
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239 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
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240 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
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241 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
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242 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
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243 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
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244
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245 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
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246 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
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247 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
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248 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
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249 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
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250 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
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251 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
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252 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
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253
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254 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
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255 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
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256 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
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257 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
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258 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
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259 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
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260 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
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261 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
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262
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83
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263 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
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264 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
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265 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
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266 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
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267 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
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268 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
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269 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
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270 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
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0
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271
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272
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83
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273 //===----------------------------------------------------------------------===//
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274 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
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275 // result from the accumulator.
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276 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
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277 //===----------------------------------------------------------------------===//
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278
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279 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
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280 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
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281 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
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282 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
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283 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
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284 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
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285 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
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286 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
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0
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287
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83
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288 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
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289 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
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290 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
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291 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
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292 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
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293 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
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294 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
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295 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
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0
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296
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83
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297 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
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298 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
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299 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
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300 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
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301 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
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302 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
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303 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
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304 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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305
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83
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306 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
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307 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
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308 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
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309 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
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310 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
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311 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
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312 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
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313 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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314
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83
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315 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
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316 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
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317 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
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318 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
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319 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
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320 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
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321 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
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322 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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323
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83
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324 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
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325 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
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326 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
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327 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
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328 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
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329 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
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330 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
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331 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
332
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
333
|
|
83
|
334 //===----------------------------------------------------------------------===//
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335 // Multiply signed/unsigned halfwords with and without saturation and rounding
|
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336 // into a 64-bits destination register.
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337 //===----------------------------------------------------------------------===//
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
338
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|
83
|
339 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
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340 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
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341 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
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342 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
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343 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
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344 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
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345 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
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346 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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347
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83
|
348 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
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349 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
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350 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
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351 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
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352 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
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353 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
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354 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
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355 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
356
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83
|
357 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
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358 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
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359 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
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360 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
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361 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
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362 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
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363 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
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364 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365
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83
|
366 //===----------------------------------------------------------------------===//
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367 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
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368 // result from the 64-bit destination register.
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369 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
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370 //===----------------------------------------------------------------------===//
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
371
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83
|
372 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
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373 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
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374 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
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375 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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376
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83
|
377 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
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378 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
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379 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
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380 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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381
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83
|
382 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
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383 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
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384 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
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385 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386
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83
|
387 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
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388 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
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389 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
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390 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
391
|
|
83
|
392 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
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393 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
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394 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
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395 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396
|
|
83
|
397 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
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|
|
398 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
|
|
|
399 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
|
|
|
400 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
401
|
|
83
|
402 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
|
|
|
403 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
|
|
|
404 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
|
|
|
405 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406
|
|
83
|
407 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
|
|
|
408 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
|
|
|
409 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
|
|
|
410 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411
|
|
83
|
412 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
|
|
|
413 def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>;
|
|
|
414 def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415
|
|
83
|
416 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
|
|
|
417 def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>;
|
|
|
418 def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
419
|
|
83
|
420 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
|
|
|
421 def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>;
|
|
|
422 def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
423
|
|
83
|
424 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
|
|
|
425 def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>;
|
|
|
426 def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
427
|
|
83
|
428 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
429 def : T_PP_pat <M2_mmpyh_s0, int_hexagon_M2_mmpyh_s0>;
|
|
|
430 def : T_PP_pat <M2_mmpyh_s1, int_hexagon_M2_mmpyh_s1>;
|
|
|
431 def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>;
|
|
|
432 def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433
|
|
83
|
434 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
435 def : T_PP_pat <M2_mmpyl_s0, int_hexagon_M2_mmpyl_s0>;
|
|
|
436 def : T_PP_pat <M2_mmpyl_s1, int_hexagon_M2_mmpyl_s1>;
|
|
|
437 def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>;
|
|
|
438 def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439
|
|
83
|
440 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
441 def : T_PP_pat <M2_mmpyuh_s0, int_hexagon_M2_mmpyuh_s0>;
|
|
|
442 def : T_PP_pat <M2_mmpyuh_s1, int_hexagon_M2_mmpyuh_s1>;
|
|
|
443 def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>;
|
|
|
444 def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445
|
|
83
|
446 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
447 def : T_PP_pat <M2_mmpyul_s0, int_hexagon_M2_mmpyul_s0>;
|
|
|
448 def : T_PP_pat <M2_mmpyul_s1, int_hexagon_M2_mmpyul_s1>;
|
|
|
449 def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>;
|
|
|
450 def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451
|
|
83
|
452 // Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32)
|
|
|
453 def : T_PP_pat <A2_vraddub, int_hexagon_A2_vraddub>;
|
|
|
454 def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455
|
|
83
|
456 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
|
|
|
457 def : T_PP_pat <A2_vrsadub, int_hexagon_A2_vrsadub>;
|
|
|
458 def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>;
|
|
|
459
|
|
|
460 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
|
|
|
461 def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
462
|
|
83
|
463 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
|
|
|
464 def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465
|
|
83
|
466 // Vector reduce complex multiply real or imaginary:
|
|
|
467 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
|
|
|
468 def : T_PP_pat <M2_vrcmpyi_s0, int_hexagon_M2_vrcmpyi_s0>;
|
|
|
469 def : T_PP_pat <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>;
|
|
|
470 def : T_PPP_pat <M2_vrcmaci_s0, int_hexagon_M2_vrcmaci_s0>;
|
|
|
471 def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472
|
|
83
|
473 def : T_PP_pat <M2_vrcmpyr_s0, int_hexagon_M2_vrcmpyr_s0>;
|
|
|
474 def : T_PP_pat <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>;
|
|
|
475 def : T_PPP_pat <M2_vrcmacr_s0, int_hexagon_M2_vrcmacr_s0>;
|
|
|
476 def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477
|
|
83
|
478 // Vector reduce halfwords
|
|
|
479 // Rdd[+]=vrmpyh(Rss,Rtt)
|
|
|
480 def : T_PP_pat <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>;
|
|
|
481 def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
482
|
|
83
|
483 //===----------------------------------------------------------------------===//
|
|
|
484 // Vector Multipy with accumulation
|
|
|
485 //===----------------------------------------------------------------------===//
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
486
|
|
83
|
487 // Vector multiply word by signed half with accumulation
|
|
|
488 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
489 def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>;
|
|
|
490 def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>;
|
|
|
491 def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>;
|
|
|
492 def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>;
|
|
|
493 def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>;
|
|
|
494 def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>;
|
|
|
495 def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>;
|
|
|
496 def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
497
|
|
83
|
498 // Vector multiply word by unsigned half with accumulation
|
|
|
499 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
|
|
|
500 def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>;
|
|
|
501 def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>;
|
|
|
502 def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>;
|
|
|
503 def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>;
|
|
|
504 def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>;
|
|
|
505 def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>;
|
|
|
506 def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>;
|
|
|
507 def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
508
|
|
83
|
509 // Vector multiply even halfwords with accumulation
|
|
|
510 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
|
|
|
511 def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>;
|
|
|
512 def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>;
|
|
|
513 def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514
|
|
83
|
515 // Vector dual multiply with accumulation
|
|
|
516 // Rxx+=vdmpy(Rss,Rtt)[:sat]
|
|
|
517 def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>;
|
|
|
518 def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519
|
|
83
|
520 // Vector complex multiply real or imaginary with accumulation
|
|
|
521 // Rxx+=vcmpy[ir](Rss,Rtt):sat
|
|
|
522 def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>;
|
|
|
523 def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
524
|
|
83
|
525 //===----------------------------------------------------------------------===//
|
|
|
526 // Add/Subtract halfword
|
|
|
527 // Rd=add(Rt.L,Rs.[HL])[:sat]
|
|
|
528 // Rd=sub(Rt.L,Rs.[HL])[:sat]
|
|
|
529 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
|
|
|
530 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
|
|
|
531 //===----------------------------------------------------------------------===//
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532
|
|
83
|
533 //Rd=add(Rt.L,Rs.[LH])
|
|
|
534 def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>;
|
|
|
535 def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
536
|
|
83
|
537 //Rd=add(Rt.L,Rs.[LH]):sat
|
|
|
538 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
|
|
|
539 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
540
|
|
83
|
541 //Rd=sub(Rt.L,Rs.[LH])
|
|
|
542 def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>;
|
|
|
543 def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
544
|
|
83
|
545 //Rd=sub(Rt.L,Rs.[LH]):sat
|
|
|
546 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
|
|
|
547 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
548
|
|
83
|
549 //Rd=add(Rt.[LH],Rs.[LH]):<<16
|
|
|
550 def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>;
|
|
|
551 def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>;
|
|
|
552 def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>;
|
|
|
553 def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
554
|
|
83
|
555 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
|
|
|
556 def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>;
|
|
|
557 def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>;
|
|
|
558 def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>;
|
|
|
559 def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
560
|
|
83
|
561 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
|
|
|
562 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
|
|
|
563 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
|
|
|
564 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
|
|
|
565 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
566
|
|
83
|
567 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
|
|
|
568 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
|
|
|
569 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
|
|
|
570 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
|
|
|
571 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
572
|
|
83
|
573 // ALU64 / ALU / min max
|
|
|
574 def : T_RR_pat<A2_max, int_hexagon_A2_max>;
|
|
|
575 def : T_RR_pat<A2_min, int_hexagon_A2_min>;
|
|
|
576 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
|
|
|
577 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
578
|
|
83
|
579 // Shift and accumulate
|
|
|
580 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
|
|
|
581 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
|
|
|
582 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
|
|
|
583 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
|
|
|
584 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
|
|
|
585 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
586
|
|
83
|
587 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
|
|
|
588 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
|
|
|
589 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
|
|
|
590 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
|
|
|
591 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
|
|
|
592 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
|
|
|
593 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
|
|
|
594 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
595
|
|
83
|
596 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
|
|
|
597 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
|
|
|
598 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
|
|
|
599 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
|
|
|
600 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
|
|
|
601 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
602
|
|
83
|
603 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
|
|
|
604 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
|
|
|
605 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
|
|
|
606 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
|
|
|
607 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
|
|
|
608 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
|
|
|
609 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
|
|
|
610 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
611
|
|
83
|
612 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
|
|
|
613 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
|
|
|
614 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
|
|
|
615 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
|
|
|
616 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
|
|
|
617 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
|
|
|
618 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
|
|
|
619 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
620
|
|
83
|
621 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
|
|
|
622 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
|
|
|
623 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
|
|
|
624 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
|
|
|
625 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
|
|
|
626 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
|
|
|
627 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
|
|
|
628 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
629
|
|
83
|
630 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
|
|
|
631 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
|
|
|
632 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
|
|
|
633 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
|
|
|
634 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
|
|
|
635 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
|
|
|
636 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
|
|
|
637 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
638
|
|
83
|
639 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
|
|
|
640 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
|
|
|
641 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
|
|
|
642 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
|
|
|
643 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
|
|
|
644 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
|
|
|
645 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
|
|
|
646 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
647
|
|
83
|
648 def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>;
|
|
|
649 def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>;
|
|
|
650 def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>;
|
|
|
651 def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>;
|
|
|
652 def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>;
|
|
|
653 def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
654
|
|
83
|
655 def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>;
|
|
|
656 def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>;
|
|
|
657 def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>;
|
|
|
658 def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>;
|
|
|
659 def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>;
|
|
|
660 def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>;
|
|
|
661 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
|
|
|
662 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
663
|
|
83
|
664 def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>;
|
|
|
665 def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>;
|
|
|
666 def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>;
|
|
|
667 def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>;
|
|
|
668 def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>;
|
|
|
669 def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
670
|
|
83
|
671 def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>;
|
|
|
672 def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>;
|
|
|
673 def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>;
|
|
|
674 def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>;
|
|
|
675 def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>;
|
|
|
676 def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>;
|
|
|
677 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
|
|
|
678 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
679
|
|
83
|
680 def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>;
|
|
|
681 def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>;
|
|
|
682 def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>;
|
|
|
683 def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>;
|
|
|
684 def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>;
|
|
|
685 def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>;
|
|
|
686 def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>;
|
|
|
687 def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
688
|
|
83
|
689 def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>;
|
|
|
690 def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>;
|
|
|
691 def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>;
|
|
|
692 def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>;
|
|
|
693 def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>;
|
|
|
694 def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>;
|
|
|
695 def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>;
|
|
|
696 def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
697
|
|
83
|
698 def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>;
|
|
|
699 def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>;
|
|
|
700 def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>;
|
|
|
701 def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>;
|
|
|
702 def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>;
|
|
|
703 def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>;
|
|
|
704 def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>;
|
|
|
705 def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
706
|
|
83
|
707 def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>;
|
|
|
708 def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>;
|
|
|
709 def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>;
|
|
|
710 def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>;
|
|
|
711 def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>;
|
|
|
712 def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>;
|
|
|
713 def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>;
|
|
|
714 def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
715
|
|
120
|
716 //*******************************************************************
|
|
|
717 // ALU32/ALU
|
|
|
718 //*******************************************************************
|
|
83
|
719 def : T_RR_pat<A2_add, int_hexagon_A2_add>;
|
|
|
720 def : T_RI_pat<A2_addi, int_hexagon_A2_addi>;
|
|
|
721 def : T_RR_pat<A2_sub, int_hexagon_A2_sub>;
|
|
|
722 def : T_IR_pat<A2_subri, int_hexagon_A2_subri>;
|
|
|
723 def : T_RR_pat<A2_and, int_hexagon_A2_and>;
|
|
|
724 def : T_RI_pat<A2_andir, int_hexagon_A2_andir>;
|
|
|
725 def : T_RR_pat<A2_or, int_hexagon_A2_or>;
|
|
|
726 def : T_RI_pat<A2_orir, int_hexagon_A2_orir>;
|
|
|
727 def : T_RR_pat<A2_xor, int_hexagon_A2_xor>;
|
|
|
728 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
729
|
|
83
|
730 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
|
|
120
|
731 def : Pat <(int_hexagon_A2_not I32:$Rs),
|
|
|
732 (A2_subri -1, I32:$Rs)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
733
|
|
83
|
734 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
|
|
120
|
735 def : Pat <(int_hexagon_A2_neg I32:$Rs),
|
|
|
736 (A2_subri 0, I32:$Rs)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
737
|
|
134
|
738 // Make sure the patterns with zero immediate value has higher complexity
|
|
|
739 // otherwise, we need to updated the predicates for immediates to exclude zero
|
|
|
740 let AddedComplexity = 200 in {
|
|
|
741 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)),
|
|
|
742 (A2_tfr I32:$Rs)>;
|
|
|
743 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)),
|
|
|
744 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
|
|
|
745 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)),
|
|
|
746 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
|
|
|
747 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)),
|
|
|
748 (S2_vsathub I64:$Rs)>;
|
|
|
749 }
|
|
|
750
|
|
|
751 def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm),
|
|
|
752 (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>;
|
|
|
753 def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm),
|
|
|
754 (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>;
|
|
|
755 def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
|
|
|
756 (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
|
|
|
757 def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm),
|
|
|
758 (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>;
|
|
|
759
|
|
83
|
760 // Transfer immediate
|
|
120
|
761 def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is),
|
|
|
762 (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>;
|
|
|
763 def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is),
|
|
|
764 (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
765
|
|
83
|
766 // Transfer Register/immediate.
|
|
|
767 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
|
|
|
768 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
|
|
120
|
769
|
|
|
770 def ImmExt64: SDNodeXForm<imm, [{
|
|
|
771 int64_t V = N->getSExtValue();
|
|
|
772 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64);
|
|
|
773 }]>;
|
|
|
774
|
|
|
775 // A2_tfrpi has an operand of type i64. This is necessary, since it is
|
|
|
776 // generated from "(set I64:$Rd, imm)". That pattern would not appear
|
|
|
777 // in the DAG, if the immediate was not a 64-bit value.
|
|
|
778 // The builtin for A2_tfrpi, on the other hand, takes a 32-bit value,
|
|
|
779 // which makes it impossible to simply replace it with the instruction.
|
|
|
780 // To connect the builtin with the instruction, the builtin's operand
|
|
|
781 // needs to be extended to the right type.
|
|
|
782
|
|
|
783 def : Pat<(int_hexagon_A2_tfrpi imm:$Is),
|
|
|
784 (A2_tfrpi (ImmExt64 $Is))>;
|
|
83
|
785
|
|
|
786 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
|
|
120
|
787 def : Pat<(int_hexagon_A2_tfrp I64:$src),
|
|
|
788 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
789
|
|
120
|
790 //*******************************************************************
|
|
|
791 // ALU32/PERM
|
|
|
792 //*******************************************************************
|
|
83
|
793 // Combine
|
|
|
794 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
|
|
|
795 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
|
|
|
796 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
|
|
|
797 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
798
|
|
120
|
799 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32_0ImmPred, s8_0ImmPred>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
800
|
|
83
|
801 // Mux
|
|
120
|
802 def : T_QRR_pat<C2_mux, int_hexagon_C2_mux>;
|
|
|
803 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32_0ImmPred>;
|
|
|
804 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32_0ImmPred>;
|
|
|
805 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
806
|
|
83
|
807 // Shift halfword
|
|
|
808 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
|
|
|
809 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
|
|
|
810 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
811
|
|
83
|
812 // Sign/zero extend
|
|
|
813 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
|
|
|
814 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
|
|
|
815 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
|
|
|
816 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
817
|
|
120
|
818 //*******************************************************************
|
|
|
819 // ALU32/PRED
|
|
|
820 //*******************************************************************
|
|
83
|
821 // Compare
|
|
120
|
822 def : T_Q_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
|
|
|
823 def : T_Q_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
|
|
|
824 def : T_Q_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
825
|
|
120
|
826 def : T_Q_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32_0ImmPred>;
|
|
|
827 def : T_Q_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32_0ImmPred>;
|
|
|
828 def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32_0ImmPred>;
|
|
83
|
829
|
|
120
|
830 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2),
|
|
|
831 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
|
|
83
|
832
|
|
120
|
833 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred:$src2),
|
|
|
834 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
|
|
83
|
835
|
|
120
|
836 def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0),
|
|
|
837 (C2_tfrpr (C2_cmpeq I32:$src, I32:$src))>;
|
|
|
838 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
|
|
|
839 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
|
|
|
840 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
|
|
|
841 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
|
|
83
|
842
|
|
120
|
843 //*******************************************************************
|
|
|
844 // ALU32/VH
|
|
|
845 //*******************************************************************
|
|
83
|
846 // Vector add, subtract, average halfwords
|
|
|
847 def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>;
|
|
|
848 def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>;
|
|
|
849 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
850
|
|
83
|
851 def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>;
|
|
|
852 def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>;
|
|
|
853 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
854
|
|
83
|
855 def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>;
|
|
|
856 def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>;
|
|
|
857 def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
858
|
|
120
|
859 //*******************************************************************
|
|
|
860 // ALU64/ALU
|
|
|
861 //*******************************************************************
|
|
|
862 def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>;
|
|
|
863 def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>;
|
|
|
864 def: T_PP_pat<A2_addp, int_hexagon_A2_addp>;
|
|
|
865 def: T_PP_pat<A2_subp, int_hexagon_A2_subp>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
866
|
|
120
|
867 def: T_PP_pat<A2_andp, int_hexagon_A2_andp>;
|
|
|
868 def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
|
|
|
869 def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
870
|
|
120
|
871 def: T_Q_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>;
|
|
|
872 def: T_Q_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>;
|
|
|
873 def: T_Q_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
874
|
|
120
|
875 def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
|
|
|
876 def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
877
|
|
120
|
878 //*******************************************************************
|
|
|
879 // ALU64/VB
|
|
|
880 //*******************************************************************
|
|
83
|
881 // ALU64 - Vector add
|
|
|
882 def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>;
|
|
|
883 def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>;
|
|
|
884 def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>;
|
|
|
885 def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>;
|
|
|
886 def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>;
|
|
|
887 def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>;
|
|
|
888 def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
889
|
|
83
|
890 // ALU64 - Vector average
|
|
|
891 def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>;
|
|
|
892 def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>;
|
|
|
893 def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>;
|
|
|
894 def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>;
|
|
|
895 def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>;
|
|
|
896 def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>;
|
|
|
897 def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
898
|
|
83
|
899 def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>;
|
|
|
900 def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>;
|
|
|
901 def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>;
|
|
|
902 def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>;
|
|
|
903 def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>;
|
|
|
904
|
|
|
905 // ALU64 - Vector negative average
|
|
|
906 def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>;
|
|
|
907 def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>;
|
|
|
908 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
|
|
|
909 def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>;
|
|
|
910 def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>;
|
|
|
911 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
912
|
|
83
|
913 // ALU64 - Vector max
|
|
|
914 def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>;
|
|
|
915 def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>;
|
|
|
916 def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>;
|
|
|
917 def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>;
|
|
|
918 def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>;
|
|
|
919
|
|
|
920 // ALU64 - Vector min
|
|
|
921 def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>;
|
|
|
922 def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>;
|
|
|
923 def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>;
|
|
|
924 def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>;
|
|
|
925 def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
926
|
|
83
|
927 // ALU64 - Vector sub
|
|
|
928 def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>;
|
|
|
929 def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>;
|
|
|
930 def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>;
|
|
|
931 def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>;
|
|
|
932 def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>;
|
|
|
933 def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>;
|
|
|
934 def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
935
|
|
83
|
936 // ALU64 - Vector compare bytes
|
|
120
|
937 def : T_Q_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>;
|
|
|
938 def : T_Q_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>;
|
|
|
939 def : T_Q_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
|
|
83
|
940
|
|
|
941 // ALU64 - Vector compare halfwords
|
|
120
|
942 def : T_Q_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>;
|
|
|
943 def : T_Q_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>;
|
|
|
944 def : T_Q_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
|
|
83
|
945
|
|
|
946 // ALU64 - Vector compare words
|
|
120
|
947 def : T_Q_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>;
|
|
|
948 def : T_Q_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>;
|
|
|
949 def : T_Q_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
950
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
951 // ALU64 / VB / Vector mux.
|
|
120
|
952 def : T_QPP_pat <C2_vmux, int_hexagon_C2_vmux>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
953
|
|
83
|
954 // MPY - Multiply and use full result
|
|
|
955 // Rdd = mpy[u](Rs, Rt)
|
|
|
956 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
|
|
|
957 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
958
|
|
83
|
959 // Complex multiply real or imaginary
|
|
|
960 def : T_RR_pat <M2_cmpyi_s0, int_hexagon_M2_cmpyi_s0>;
|
|
|
961 def : T_RR_pat <M2_cmpyr_s0, int_hexagon_M2_cmpyr_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
962
|
|
83
|
963 // Complex multiply
|
|
|
964 def : T_RR_pat <M2_cmpys_s0, int_hexagon_M2_cmpys_s0>;
|
|
|
965 def : T_RR_pat <M2_cmpysc_s0, int_hexagon_M2_cmpysc_s0>;
|
|
|
966 def : T_RR_pat <M2_cmpys_s1, int_hexagon_M2_cmpys_s1>;
|
|
|
967 def : T_RR_pat <M2_cmpysc_s1, int_hexagon_M2_cmpysc_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
968
|
|
83
|
969 // Vector multiply halfwords
|
|
|
970 // Rdd=vmpyh(Rs,Rt)[:<<1]:sat
|
|
|
971 def : T_RR_pat <M2_vmpy2s_s0, int_hexagon_M2_vmpy2s_s0>;
|
|
|
972 def : T_RR_pat <M2_vmpy2s_s1, int_hexagon_M2_vmpy2s_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
973
|
|
83
|
974 // Rxx[+-]= mpy[u](Rs,Rt)
|
|
|
975 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
|
|
|
976 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
|
|
|
977 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
|
|
|
978 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
979
|
|
83
|
980 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
|
|
|
981 def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>;
|
|
|
982 def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>;
|
|
|
983 def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>;
|
|
|
984 def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
985
|
|
83
|
986 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
|
|
|
987 def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>;
|
|
|
988 def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>;
|
|
|
989 def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>;
|
|
|
990 def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
991
|
|
83
|
992 // Rxx+=cmpy[ir](Rs,Rt)
|
|
|
993 def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>;
|
|
|
994 def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
995
|
|
83
|
996 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
|
|
|
997 def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>;
|
|
|
998 def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>;
|
|
|
999 def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1000
|
|
120
|
1001 //*******************************************************************
|
|
|
1002 // CR
|
|
|
1003 //*******************************************************************
|
|
|
1004 def: T_Q_Q_pat<C2_not, int_hexagon_C2_not>;
|
|
|
1005 def: T_Q_Q_pat<C2_all8, int_hexagon_C2_all8>;
|
|
|
1006 def: T_Q_Q_pat<C2_any8, int_hexagon_C2_any8>;
|
|
|
1007 def: T_Q_Q_pat<C2_pxfer_map, int_hexagon_C2_pxfer_map>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1008
|
|
120
|
1009 def: T_Q_QQ_pat<C2_and, int_hexagon_C2_and>;
|
|
|
1010 def: T_Q_QQ_pat<C2_andn, int_hexagon_C2_andn>;
|
|
|
1011 def: T_Q_QQ_pat<C2_or, int_hexagon_C2_or>;
|
|
|
1012 def: T_Q_QQ_pat<C2_orn, int_hexagon_C2_orn>;
|
|
|
1013 def: T_Q_QQ_pat<C2_xor, int_hexagon_C2_xor>;
|
|
95
|
1014
|
|
83
|
1015 // Multiply 32x32 and use lower result
|
|
|
1016 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
|
|
|
1017 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
|
|
120
|
1018 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1019
|
|
83
|
1020 // Subtract and accumulate
|
|
|
1021 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1022
|
|
83
|
1023 // Add and accumulate
|
|
|
1024 def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>;
|
|
|
1025 def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>;
|
|
|
1026 def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>;
|
|
|
1027 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1028
|
|
83
|
1029 // XOR and XOR with destination
|
|
|
1030 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1031
|
|
83
|
1032 // Vector dual multiply with round and pack
|
|
120
|
1033 def : T_PP_pat <M2_vdmpyrs_s0, int_hexagon_M2_vdmpyrs_s0>;
|
|
|
1034 def : T_PP_pat <M2_vdmpyrs_s1, int_hexagon_M2_vdmpyrs_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1035
|
|
83
|
1036 // Vector multiply halfwords with round and pack
|
|
120
|
1037 def : T_RR_pat <M2_vmpy2s_s0pack, int_hexagon_M2_vmpy2s_s0pack>;
|
|
|
1038 def : T_RR_pat <M2_vmpy2s_s1pack, int_hexagon_M2_vmpy2s_s1pack>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1039
|
|
83
|
1040 // Multiply and use lower result
|
|
120
|
1041 def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyi>;
|
|
|
1042 def : T_RI_pat <M2_mpysmi, int_hexagon_M2_mpysmi>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1043
|
|
83
|
1044 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
|
|
120
|
1045 def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyui>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1046
|
|
83
|
1047 // Multiply and use upper result
|
|
120
|
1048 def : T_RR_pat <M2_mpy_up, int_hexagon_M2_mpy_up>;
|
|
|
1049 def : T_RR_pat <M2_mpyu_up, int_hexagon_M2_mpyu_up>;
|
|
|
1050 def : T_RR_pat <M2_hmmpyh_rs1, int_hexagon_M2_hmmpyh_rs1>;
|
|
|
1051 def : T_RR_pat <M2_hmmpyl_rs1, int_hexagon_M2_hmmpyl_rs1>;
|
|
|
1052 def : T_RR_pat <M2_dpmpyss_rnd_s0, int_hexagon_M2_dpmpyss_rnd_s0>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1053
|
|
83
|
1054 // Complex multiply with round and pack
|
|
|
1055 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
|
|
120
|
1056 def : T_RR_pat <M2_cmpyrs_s0, int_hexagon_M2_cmpyrs_s0>;
|
|
|
1057 def : T_RR_pat <M2_cmpyrs_s1, int_hexagon_M2_cmpyrs_s1>;
|
|
|
1058 def : T_RR_pat <M2_cmpyrsc_s0, int_hexagon_M2_cmpyrsc_s0>;
|
|
|
1059 def : T_RR_pat <M2_cmpyrsc_s1, int_hexagon_M2_cmpyrsc_s1>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1060
|
|
120
|
1061 //*******************************************************************
|
|
|
1062 // STYPE/ALU
|
|
|
1063 //*******************************************************************
|
|
83
|
1064 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
|
|
|
1065 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
|
|
|
1066 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1067
|
|
120
|
1068 //*******************************************************************
|
|
|
1069 // STYPE/BIT
|
|
|
1070 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1071
|
|
83
|
1072 // Count leading/trailing
|
|
|
1073 def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>;
|
|
|
1074 def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>;
|
|
|
1075 def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>;
|
|
|
1076 def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>;
|
|
|
1077 def: T_R_pat<S2_clb, int_hexagon_S2_clb>;
|
|
|
1078 def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>;
|
|
|
1079 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
|
|
|
1080 def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>;
|
|
|
1081 def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>;
|
|
|
1082
|
|
|
1083 // Compare bit mask
|
|
|
1084 def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>;
|
|
|
1085 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
|
|
|
1086 def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1087
|
|
83
|
1088 // Vector shuffle
|
|
|
1089 def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>;
|
|
|
1090 def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>;
|
|
|
1091 def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>;
|
|
|
1092 def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>;
|
|
|
1093
|
|
|
1094 // Vector truncate
|
|
|
1095 def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>;
|
|
|
1096 def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1097
|
|
83
|
1098 // Linear feedback-shift Iteration.
|
|
|
1099 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1100
|
|
120
|
1101 // Vector align
|
|
|
1102 // Need custom lowering
|
|
|
1103 def : T_PPQ_pat <S2_valignrb, int_hexagon_S2_valignrb>;
|
|
|
1104 def : T_PPI_pat <S2_valignib, int_hexagon_S2_valignib>;
|
|
|
1105
|
|
83
|
1106 // Vector splice
|
|
|
1107 def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>;
|
|
|
1108 def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>;
|
|
|
1109
|
|
|
1110 // Shift by immediate and add
|
|
|
1111 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1112
|
|
83
|
1113 // Extract bitfield
|
|
|
1114 def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>;
|
|
|
1115 def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>;
|
|
|
1116 def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>;
|
|
|
1117 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1118
|
|
83
|
1119 // Insert bitfield
|
|
120
|
1120 def : Pat <(int_hexagon_S2_insert_rp I32:$src1, I32:$src2, I64:$src3),
|
|
|
1121 (S2_insert_rp I32:$src1, I32:$src2, I64:$src3)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1122
|
|
120
|
1123 def : Pat<(i64 (int_hexagon_S2_insertp_rp I64:$src1, I64:$src2, I64:$src3)),
|
|
|
1124 (i64 (S2_insertp_rp I64:$src1, I64:$src2, I64:$src3))>;
|
|
83
|
1125
|
|
120
|
1126 def : Pat<(int_hexagon_S2_insert I32:$src1, I32:$src2,
|
|
|
1127 u5_0ImmPred:$src3, u5_0ImmPred:$src4),
|
|
|
1128 (S2_insert I32:$src1, I32:$src2,
|
|
|
1129 u5_0ImmPred:$src3, u5_0ImmPred:$src4)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1130
|
|
120
|
1131 def : Pat<(i64 (int_hexagon_S2_insertp I64:$src1, I64:$src2,
|
|
|
1132 u6_0ImmPred:$src3, u6_0ImmPred:$src4)),
|
|
|
1133 (i64 (S2_insertp I64:$src1, I64:$src2,
|
|
|
1134 u6_0ImmPred:$src3, u6_0ImmPred:$src4))>;
|
|
83
|
1135
|
|
|
1136 // Innterleave/deinterleave
|
|
|
1137 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
|
|
|
1138 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1139
|
|
83
|
1140 // Set/Clear/Toggle Bit
|
|
|
1141 def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>;
|
|
|
1142 def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>;
|
|
|
1143 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1144
|
|
83
|
1145 def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>;
|
|
|
1146 def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>;
|
|
|
1147 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1148
|
|
83
|
1149 // Test Bit
|
|
120
|
1150 def: T_Q_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>;
|
|
|
1151 def: T_Q_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1152
|
|
120
|
1153 //*******************************************************************
|
|
|
1154 // STYPE/COMPLEX
|
|
|
1155 //*******************************************************************
|
|
83
|
1156 // Vector Complex conjugate
|
|
|
1157 def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1158
|
|
83
|
1159 // Vector Complex rotate
|
|
|
1160 def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1161
|
|
120
|
1162 //*******************************************************************
|
|
|
1163 // STYPE/PERM
|
|
|
1164 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1165
|
|
83
|
1166 // Vector saturate without pack
|
|
|
1167 def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>;
|
|
|
1168 def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>;
|
|
|
1169 def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>;
|
|
|
1170 def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1171
|
|
120
|
1172 //*******************************************************************
|
|
|
1173 // STYPE/PRED
|
|
|
1174 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1175
|
|
83
|
1176 // Predicate transfer
|
|
120
|
1177 def: Pat<(i32 (int_hexagon_C2_tfrpr I32:$Rs)),
|
|
|
1178 (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>;
|
|
|
1179 def: Pat<(i32 (int_hexagon_C2_tfrrp I32:$Rs)),
|
|
|
1180 (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1181
|
|
83
|
1182 // Mask generate from predicate
|
|
120
|
1183 def: Pat<(i64 (int_hexagon_C2_mask I32:$Rs)),
|
|
|
1184 (i64 (C2_mask (C2_tfrrp I32:$Rs)))>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1185
|
|
83
|
1186 // Viterbi pack even and odd predicate bits
|
|
120
|
1187 def: T_QQ_pat<C2_vitpack, int_hexagon_C2_vitpack>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1188
|
|
120
|
1189 //*******************************************************************
|
|
|
1190 // STYPE/SHIFT
|
|
|
1191 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1192
|
|
83
|
1193 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
|
|
|
1194 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
|
|
|
1195 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1196
|
|
83
|
1197 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
|
|
|
1198 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
|
|
|
1199 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
|
|
|
1200 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1201
|
|
83
|
1202 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
|
|
|
1203 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
|
|
|
1204 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
|
|
|
1205 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
|
|
|
1206
|
|
|
1207 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
|
|
|
1208 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1209
|
|
83
|
1210 def : T_R_pat <S2_vsxtbh, int_hexagon_S2_vsxtbh>;
|
|
|
1211 def : T_R_pat <S2_vzxtbh, int_hexagon_S2_vzxtbh>;
|
|
|
1212 def : T_R_pat <S2_vsxthw, int_hexagon_S2_vsxthw>;
|
|
|
1213 def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>;
|
|
|
1214 def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>;
|
|
|
1215 def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1216
|
|
83
|
1217 // Vector saturate and pack
|
|
|
1218 def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>;
|
|
|
1219 def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>;
|
|
|
1220 def : T_P_pat <S2_vsathub, int_hexagon_S2_vsathub>;
|
|
|
1221 def : T_P_pat <S2_vsatwh, int_hexagon_S2_vsatwh>;
|
|
|
1222 def : T_P_pat <S2_vsatwuh, int_hexagon_S2_vsatwuh>;
|
|
|
1223 def : T_P_pat <S2_vsathb, int_hexagon_S2_vsathb>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1224
|
|
83
|
1225 def : T_P_pat <S2_vtrunohb, int_hexagon_S2_vtrunohb>;
|
|
|
1226 def : T_P_pat <S2_vtrunehb, int_hexagon_S2_vtrunehb>;
|
|
|
1227 def : T_P_pat <S2_vrndpackwh, int_hexagon_S2_vrndpackwh>;
|
|
|
1228 def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>;
|
|
|
1229 def : T_R_pat <S2_brev, int_hexagon_S2_brev>;
|
|
|
1230 def : T_R_pat <S2_vsplatrb, int_hexagon_S2_vsplatrb>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1231
|
|
83
|
1232 def : T_R_pat <A2_abs, int_hexagon_A2_abs>;
|
|
|
1233 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
|
|
|
1234 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1235
|
|
83
|
1236 def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1237
|
|
83
|
1238 def : T_P_pat <A2_sat, int_hexagon_A2_sat>;
|
|
|
1239 def : T_R_pat <A2_sath, int_hexagon_A2_sath>;
|
|
|
1240 def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>;
|
|
|
1241 def : T_R_pat <A2_satub, int_hexagon_A2_satub>;
|
|
|
1242 def : T_R_pat <A2_satb, int_hexagon_A2_satb>;
|
|
|
1243
|
|
|
1244 // Vector arithmetic shift right by immediate with truncate and pack.
|
|
|
1245 def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1246
|
|
83
|
1247 def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>;
|
|
|
1248 def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>;
|
|
|
1249 def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>;
|
|
|
1250 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
|
|
|
1251 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
|
|
|
1252 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1253
|
|
83
|
1254 // Shift left by immediate with saturation.
|
|
|
1255 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1256
|
|
83
|
1257 //===----------------------------------------------------------------------===//
|
|
|
1258 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
|
|
|
1259 //===----------------------------------------------------------------------===//
|
|
|
1260 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
|
|
|
1261 SDNodeXForm XformImm>
|
|
120
|
1262 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred:$src3, u5_0ImmPred:$src4),
|
|
|
1263 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
|
|
|
1264 (XformImm u5_0ImmPred:$src4))>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1265
|
|
120
|
1266 def SDEC2 : SDNodeXForm<imm, [{
|
|
|
1267 int32_t V = N->getSExtValue();
|
|
|
1268 return CurDAG->getTargetConstant(V-2, SDLoc(N), MVT::i32);
|
|
|
1269 }]>;
|
|
|
1270
|
|
|
1271 def SDEC3 : SDNodeXForm<imm, [{
|
|
|
1272 int32_t V = N->getSExtValue();
|
|
|
1273 return CurDAG->getTargetConstant(V-3, SDLoc(N), MVT::i32);
|
|
|
1274 }]>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1275
|
|
83
|
1276 // Table Index : Extract and insert bits.
|
|
|
1277 // Map to the real hardware instructions after subtracting appropriate
|
|
|
1278 // values from the 4th input operand. Please note that subtraction is not
|
|
|
1279 // needed for int_hexagon_S2_tableidxb_goodsyntax.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1280
|
|
120
|
1281 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax I32:$src1, I32:$src2,
|
|
|
1282 u4_0ImmPred:$src3, u5_0ImmPred:$src4),
|
|
|
1283 (S2_tableidxb I32:$src1, I32:$src2,
|
|
|
1284 u4_0ImmPred:$src3, u5_0ImmPred:$src4)>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1285
|
|
83
|
1286 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
|
|
120
|
1287 SDEC1>;
|
|
83
|
1288 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
|
|
120
|
1289 SDEC2>;
|
|
83
|
1290 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
|
|
120
|
1291 SDEC3>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1292
|
|
120
|
1293 //*******************************************************************
|
|
|
1294 // STYPE/VH
|
|
|
1295 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1296
|
|
83
|
1297 // Vector absolute value halfwords with and without saturation
|
|
|
1298 // Rdd64=vabsh(Rss64)[:sat]
|
|
|
1299 def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>;
|
|
|
1300 def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1301
|
|
83
|
1302 // Vector shift halfwords by immediate
|
|
|
1303 // Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4)
|
|
|
1304 def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>;
|
|
|
1305 def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>;
|
|
|
1306 def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1307
|
|
83
|
1308 // Vector shift halfwords by register
|
|
|
1309 // Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32)
|
|
|
1310 def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>;
|
|
|
1311 def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>;
|
|
|
1312 def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>;
|
|
|
1313 def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1314
|
|
120
|
1315 //*******************************************************************
|
|
|
1316 // STYPE/VW
|
|
|
1317 //*******************************************************************
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1318
|
|
83
|
1319 // Vector absolute value words with and without saturation
|
|
|
1320 def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>;
|
|
|
1321 def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1322
|
|
83
|
1323 // Vector shift words by immediate.
|
|
|
1324 // Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5)
|
|
|
1325 def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>;
|
|
|
1326 def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>;
|
|
|
1327 def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1328
|
|
83
|
1329 // Vector shift words by register.
|
|
|
1330 // Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32)
|
|
|
1331 def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>;
|
|
|
1332 def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>;
|
|
|
1333 def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>;
|
|
|
1334 def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>;
|
|
|
1335
|
|
|
1336 // Vector shift words with truncate and pack
|
|
|
1337 def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>;
|
|
|
1338
|
|
120
|
1339 // Load/store locked.
|
|
83
|
1340 def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>;
|
|
|
1341 def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1342
|
|
120
|
1343 def : Pat<(int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt),
|
|
|
1344 (C2_tfrpr (S2_storew_locked I32:$Rs, I32:$Rt))>;
|
|
|
1345 def : Pat<(int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt),
|
|
|
1346 (C2_tfrpr (S4_stored_locked I32:$Rs, I64:$Rt))>;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1347
|
|
120
|
1348 //*******************************************************************
|
|
|
1349 // ST
|
|
|
1350 //*******************************************************************
|
|
95
|
1351
|
|
|
1352 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
|
|
|
1353 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
|
|
120
|
1354 (MI I32:$Rs, I32:$Ru, Val:$Rt)>;
|
|
95
|
1355
|
|
120
|
1356 def : T_stb_pat <S2_storerh_pbr, int_hexagon_brev_sth, I32>;
|
|
|
1357 def : T_stb_pat <S2_storerb_pbr, int_hexagon_brev_stb, I32>;
|
|
|
1358 def : T_stb_pat <S2_storeri_pbr, int_hexagon_brev_stw, I32>;
|
|
|
1359 def : T_stb_pat <S2_storerf_pbr, int_hexagon_brev_sthhi, I32>;
|
|
|
1360 def : T_stb_pat <S2_storerd_pbr, int_hexagon_brev_std, I64>;
|
|
95
|
1361
|
|
|
1362 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
|
|
|
1363 : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
|
|
120
|
1364 (MI I32:$Rs, Imm:$s, I32:$Ru, Val:$Rt)>;
|
|
95
|
1365
|
|
120
|
1366 def: T_stc_pat<S2_storerb_pci, int_hexagon_circ_stb, s4_0ImmPred, I32>;
|
|
|
1367 def: T_stc_pat<S2_storerh_pci, int_hexagon_circ_sth, s4_1ImmPred, I32>;
|
|
|
1368 def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw, s4_2ImmPred, I32>;
|
|
|
1369 def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std, s4_3ImmPred, I64>;
|
|
|
1370 def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
|
|
95
|
1371
|
|
121
|
1372 multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
|
|
|
1373 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
|
|
|
1374 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>;
|
|
|
1375 def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
|
|
|
1376 HvxVR:$src3),
|
|
|
1377 (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>;
|
|
|
1378 }
|
|
|
1379
|
|
|
1380 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>;
|
|
|
1381 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>;
|
|
|
1382 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>;
|
|
|
1383 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>;
|
|
|
1384
|
|
134
|
1385 defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>;
|
|
|
1386 defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>;
|
|
|
1387 defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>;
|
|
|
1388 defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>;
|
|
|
1389
|
|
121
|
1390 //*******************************************************************
|
|
|
1391 // SYSTEM
|
|
|
1392 //*******************************************************************
|
|
|
1393
|
|
|
1394 def: T_R_pat<Y2_dccleana, int_hexagon_Y2_dccleana>;
|
|
|
1395 def: T_R_pat<Y2_dccleaninva, int_hexagon_Y2_dccleaninva>;
|
|
|
1396 def: T_R_pat<Y2_dcinva, int_hexagon_Y2_dcinva>;
|
|
|
1397 def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>;
|
|
|
1398
|
|
|
1399 def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>;
|
|
|
1400 def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>;
|
|
|
1401
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1402 include "HexagonIntrinsicsV3.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1403 include "HexagonIntrinsicsV4.td"
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1404 include "HexagonIntrinsicsV5.td"
|
|
100
|
1405 include "HexagonIntrinsicsV60.td"
|
