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comparison test/CodeGen/X86/zext-shl.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 95c75e76d11b
children 3a76565eade5
comparison
equal deleted inserted replaced
120:1172e4bd9c6f 121:803732b1fca8
1 ; RUN: llc < %s -march=x86 | FileCheck %s 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
2 3
3 define i32 @t1(i8 zeroext %x) nounwind readnone ssp { 4 define i32 @t1(i8 zeroext %x) nounwind {
4 entry:
5 ; CHECK-LABEL: t1: 5 ; CHECK-LABEL: t1:
6 ; CHECK: shll 6 ; CHECK: # BB#0:
7 ; CHECK-NOT: movzwl 7 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
8 ; CHECK: ret 8 ; CHECK-NEXT: shll $5, %eax
9 %0 = zext i8 %x to i16 9 ; CHECK-NEXT: retl
10 %1 = shl i16 %0, 5 10 %t0 = zext i8 %x to i16
11 %2 = zext i16 %1 to i32 11 %t1 = shl i16 %t0, 5
12 ret i32 %2 12 %t2 = zext i16 %t1 to i32
13 ret i32 %t2
13 } 14 }
14 15
15 define i32 @t2(i8 zeroext %x) nounwind readnone ssp { 16 define i32 @t2(i8 zeroext %x) nounwind {
16 entry:
17 ; CHECK-LABEL: t2: 17 ; CHECK-LABEL: t2:
18 ; CHECK: shrl 18 ; CHECK: # BB#0:
19 ; CHECK-NOT: movzwl 19 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
20 ; CHECK: ret 20 ; CHECK-NEXT: shrl $3, %eax
21 %0 = zext i8 %x to i16 21 ; CHECK-NEXT: retl
22 %1 = lshr i16 %0, 3 22 %t0 = zext i8 %x to i16
23 %2 = zext i16 %1 to i32 23 %t1 = lshr i16 %t0, 3
24 ret i32 %2 24 %t2 = zext i16 %t1 to i32
25 ret i32 %t2
25 } 26 }