Mercurial > hg > CbC > CbC_llvm
diff test/CodeGen/X86/zext-shl.ll @ 121:803732b1fca8
LLVM 5.0
author | kono |
---|---|
date | Fri, 27 Oct 2017 17:07:41 +0900 |
parents | 95c75e76d11b |
children | 3a76565eade5 |
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--- a/test/CodeGen/X86/zext-shl.ll Fri Nov 25 19:14:25 2016 +0900 +++ b/test/CodeGen/X86/zext-shl.ll Fri Oct 27 17:07:41 2017 +0900 @@ -1,25 +1,26 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s -define i32 @t1(i8 zeroext %x) nounwind readnone ssp { -entry: +define i32 @t1(i8 zeroext %x) nounwind { ; CHECK-LABEL: t1: -; CHECK: shll -; CHECK-NOT: movzwl -; CHECK: ret - %0 = zext i8 %x to i16 - %1 = shl i16 %0, 5 - %2 = zext i16 %1 to i32 - ret i32 %2 +; CHECK: # BB#0: +; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: shll $5, %eax +; CHECK-NEXT: retl + %t0 = zext i8 %x to i16 + %t1 = shl i16 %t0, 5 + %t2 = zext i16 %t1 to i32 + ret i32 %t2 } -define i32 @t2(i8 zeroext %x) nounwind readnone ssp { -entry: +define i32 @t2(i8 zeroext %x) nounwind { ; CHECK-LABEL: t2: -; CHECK: shrl -; CHECK-NOT: movzwl -; CHECK: ret - %0 = zext i8 %x to i16 - %1 = lshr i16 %0, 3 - %2 = zext i16 %1 to i32 - ret i32 %2 +; CHECK: # BB#0: +; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: shrl $3, %eax +; CHECK-NEXT: retl + %t0 = zext i8 %x to i16 + %t1 = lshr i16 %t0, 3 + %t2 = zext i16 %t1 to i32 + ret i32 %t2 }