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annotate test/CodeGen/X86/zext-shl.ll @ 121:803732b1fca8

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LLVM 5.0
author kono
date Fri, 27 Oct 2017 17:07:41 +0900
parents 95c75e76d11b
children 3a76565eade5
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
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4 define i32 @t1(i8 zeroext %x) nounwind {
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5 ; CHECK-LABEL: t1:
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6 ; CHECK: # BB#0:
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7 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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8 ; CHECK-NEXT: shll $5, %eax
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9 ; CHECK-NEXT: retl
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10 %t0 = zext i8 %x to i16
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11 %t1 = shl i16 %t0, 5
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12 %t2 = zext i16 %t1 to i32
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13 ret i32 %t2
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14 }
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16 define i32 @t2(i8 zeroext %x) nounwind {
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17 ; CHECK-LABEL: t2:
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18 ; CHECK: # BB#0:
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19 ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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20 ; CHECK-NEXT: shrl $3, %eax
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21 ; CHECK-NEXT: retl
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22 %t0 = zext i8 %x to i16
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23 %t1 = lshr i16 %t0, 3
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24 %t2 = zext i16 %t1 to i32
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25 ret i32 %t2
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26 }